View P32P4910_2923866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet product speci?cation 1996 may 29 integrated circuits P32P4910a prml read channel with pr4, 8/9 endec, 4-burst servo
1996 may 29 2 853-1829 16870 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a general description the philips semiconductors P32P4910a is a high performance bicmos read channel ic that provides all of the functions needed to implement an entire partial response class 4 (pr4) read channel for zoned recording hard disk drive systems with data rates from 42 to 125 mbit/s or 33 to 100 mbit/s. functional blocks include agc, programmable filter, adaptive transversal filter, viterbi qualifier, 8,9 gcr endec, data synchronizer, time base generator, and 4-burst servo. programmable functions such as data rate, filter cutoff, filter boost, etc., are controlled by writing to the serial port registers so no external component changes are required to change zones. the part requires a single +5v power supply. the philips semiconductors P32P4910a utilizes an advanced bicmos process technology along with advanced circuit design techniques which result in high performance devices with low power consumption. features general: register programmable data rates from 42 to 125 mbit/s or 33 to 100 mbit/s sampled data read channel with viterbi qualification programmable filter for pr4 equalization five tap transversal filter with adaptive pr4 equalization 8/9 gcr endec data scrambler/descrambler presettable precoder state programmable write precompensation low operating power (0.925 w typical at 5v) register programmable power management (<5 mw power down mode) 4-bit nibble and byte-wide bi-directional nrz data interfaces 8-bit direct write mode automatically configured for rclk = vco/8 serial interface port for access to internal program storage registers single power supply (5v 10%) small footprint, 100-lead lqfp package
1996 may 29 3 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a block diagram via+ via- agc amp on+ on- od+ od- cp cn dp dn level or pulse qual rds/rds ppol viterbi detector 9,8 decoder parallel interface byp hold full wave rectifier sampled agc charge pump agc control logic lowz fastrec agc charge pump conv mux vrdt test point mux tpa+ tpa- tpb+ tpb- decision directed phase detector phase/ freq detector charge pump vco rclk clock gen code word detector boundry damping control rclk sync byte detector sbd parity gen/chk nrz0-7 nrzp nibble interface vco sync pattern gen precoder write precomp wd wd dwr dwi dwi wclk mux mux perr 8,9 encoder vref sg power down control fltr2+ fltr2- pdwn serial port sden sclk sdata byps parallel to serial mux vpd1 vpd2 vpa1 vpa2 vpa3 agnd1 agnd2 agnd3 dgnd1 dgnd2 control registers data synchronizer rg wg/wg ato rr control logic vrx ato test mux dsclk dsclk dsclk fref fltr1+ fltr1- charge pump vco 1/(n+1) 1/(m+1) phase/ freq detector time base generator rclk rclk ssi 32p4910 block diagram descrambler scrambler serial to parallel sync field counter to sfc from level qual tbgout cwbd cwbd write flip-flop t 2 -adaptive equalizer 5-tap 2-prog tbgout & tpc+ tpc- eqhold chanqual chanqual tbgout asymm factor ssbyp lowz asymm factor dacs sg + - decode logic 1/12 servo leakage reset strobe a b c d maxref x2 x2 x2 x2 3.2 v ref programmable filter 7th-order low-pass asymmetric 0's hysteresis squelch dual "or" type vmin sfc tpd+ tpd- dc cancel offset full wave rectifier lowz sfc mux tpd mux tpc en agcrst ufdc vcc agcdel wrdel lzto fdto hold hold lowz squelch ufdc vrc vref automatic training & sync byte generator (0,4/4) (0,4/4) sfc maxref/2 dac servo fastrec sfwr tpe mux tpe fastrec lowz sfwr ufdc philips semiconductors P32P4910a
1996 may 29 4 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a automatic gain control: dual mode agc, analog during acquisition, sampled during data reads separate agc level storage pins for data and servo dual rate attack and decay charge pump for rapid agc recovery (analog) programmable, symmetric, charge pump currents for data reads (sampled) charge pump currents track programmable data rate during data reads (sampled) low drift agc hold circuitry low-z circuitry at agc input provides for rapid external coupling capacitor recovery agc amplifier squelch during low-z wide bandwidth, precision full-wave rectifier programmable agc controls C separate external input pins for agc hold, fast recovery, and low-z control or C internal low-z and fast decay timing for rapid transient recovery and agc acquisition. timing set with external resistors (2). ultra fast decay current set with external resistor. agc input impedance vs lowz = 5:1. 2-bit dac to control agc voltage in servo mode between 1.1 and 1.4 v filter/equalizer: programmable, 7-pole, continuous time filter provides: C channel filter and pulse slimming equalization for equalization to pr4 C programmable cutoff frequency from 4 to 34 mhz C programmable boost /equalization of 0 to 13 db C programmable "zeros" equalization provides time asymmetry compensation C 0.5 ns group delay variation from 0.3?c to ?c, with ?c = 34 mhz C minimizes size and power C low-z switch at filter output for fast offset recovery C no external coupling capacitors required C dc offset compensation provided at filter output C five tap transversal filter for fine equalization to pr4 C self adapting inner taps (symmetric) C programmable outer taps (symmetric, 4-bits) C equalization hold input C "zeros" channel quality output C amplitude asymmetry factor output pulse quali?cation: sampled viterbi qualification of signal equalized to pr4 register programmable window or hysteresis pulse qualifier for servo reads selectable rds pulse width and polarity for servo gray code reads
1996 may 29 5 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a time base generator: less than 1% frequency resolution up to 141 mhz frequency output independent m and n divide-by registers no active external components required data separator: fully integrated data separator includes data synchronizer and 8,9 gcr endec register programmable to 125 mbit/s operation fast acquisition, sampled data phase lock loop decision directed clock recovery from data samples adaptive clock recovery thresholds programmable damping ratio for data synchronizer pll is constant for all data rates data scrambler/descrambler to reduce fixed pattern effects 4-bit nibble and byte-wide nrz data interfaces time base tracking, programmable write precompensation differential pecl write data output integrated sync byte detection, single byte or dual ("or" type) semi-auto training and sync byte generation available for single sync byte operation surface defect scan mode servo: 4-burst servo capture with a, b, c, d outputs internal hold capacitors "soft landing" charge pump architecture separate, automatically selected, registers for servo ?c, boost, and threshold programmable charge pump current wide bandwidth, precision full-wave rectifier programmable selection of normal or differentiated filter output to servo capture block programmable agc gain in servo mode (2-bits) full wave rectifier observation point
1996 may 29 6 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a functional description the philips semiconductors P32P4910a implements a complete high performance pr4 read channel, including an agc, programmable filter/equalizer, adaptive transversal filter, viterbi pulse qualifier, time base generator, data separator with 8,9 endec and scrambler/descrambler, and 4-burst capture servo, that supports data rates from 42 to 125 mbit/s. data rates from 33 to 100 mbit/s are supported by changing a single resistor. a serial port is provided to write control data to the 17 internal program storage registers. agc circuit description the automatic gain control (agc) circuit is used to maintain a constant signal amplitude at the input of the pulse detector and sampled data processor while the input to the amplifier varies. the circuit consists of an agc loop that includes an agc amplifier, charge pump, programmable continuous time filter, and a precision, wide band, full wave rectifier. depending on whether the read is of servo or data type, the specific blocks utilized in the loop are slightly different. both loop paths are fully differential to minimize susceptibility to noise. agc control can be programmably selected between direct and timed modes. agc o peration in s ervo r ead m ode during servo reads the loop consists of the agc amplifier with a continuous dual rate charge pump, the programmable continuous time filter, and the full wave rectifier. the gain of the agc amplifier is controlled by the voltage stored on the byps hold capacitor (c byps ). the dual rate charge pump drives c byps with currents that drive the differential voltage at dp/dn (internal nodes) to the value programmed by the 2 sagclvl bits in the lds register. these 2 bits allow adjustment of the filter's normal output voltage from 1.10 to 1.40 vppd. attack currents lower the voltage at the byps pin which reduces the amplifier gain. decay currents raise the voltage at the byps pin which increases the amplifier gain. the sensitivity of the amplifier gain to changes in the byps voltage is approximately 38 db/v. when the voltage at byps is equal to vrc, the gain from the agc input to dp/dn will be about 24.9 db. the charge pump is continuously driven by the instantaneous voltage at dp/dn. when the signal at dp/dn is greater than 100% of the programmed agc level, the normal attack current (i ch ) of 416.5 m a is used to reduce the amplifier gain. if the signal is greater than 125% of the programmed level, the fast attack current (i chf ) of 3.5 m a is used to reduce the gain very quickly. this dual rate approach allows the agc gain to be quickly decreased when it is too high and minimizes distortion when the proper agc level has been acquired. the 100% and 125% levels are relative to the selected agc level in servo mode. a constant normal decay current (i d ) of 24.5 m a acts to increase the amplifier gain when the signal at dp/dn is less than 100% of the programmed agc level. the large ratio (416.5 m a:24.5 m a) of the normal attack and normal decay currents enables the agc loop to respond to the peak amplitudes of the incoming read signal rather than the average value. as a result the agc loop will not be able to quickly increase its gain if required to do so. a fast recovery mode is provided to allow the gain to be rapidly increased to reduce recovery time between mode switches. in the fast recovery mode, the decay current is increased by a factor of 8 to 196 m a (i dfr ) and the attack current is increased by a factor of 4.18 to 1.74 m a (i chfr ). this has the effect of speeding up the agc loop between 4 and 8 times. it is recommended that the fast recovery mode be asserted when the agc fields from a sector are being read. typically, this will be just after each transition of sg (servo gate), after powerup, and after wg/ wg is de-asserted. for example, if c byps is 500 pf and fastrec is asserted for 0.5 m s in servo mode, the voltage at byps can increase at most by 0.5 m s * 196 m a/500 pf = 196 mv, which will allow the gain to increase by 6 db in that time. if fastrec is asserted for 0.5 m s in non-servo mode and c byp is 1000 pf, then the voltage at byp can increase at most by 0.5 m s * 196 m a/ 1000 pf = 98 mv, which will allow the gain to increase by 3 db in that time. it is recommended that lowz be asserted for 0.5 m s just prior to any assertion of fastrec in order to null any internal dc offsets. however, it is possible to assert both lowz and fastrec simultaneously to reduce sector overhead. this method should be evaluated under the actual system operating conditions. the programmable agc level in servo mode is provided to allow the servo demodulator dynamic range to be adjusted over a narrow range.
1996 may 29 7 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a agc o peration in d ata r ead m ode for data reads, the loop described above is used until the data synchronizer is locked to the incoming vco preamble, except that the byp hold capacitor (c byp ) is used instead of byps and (c byps ). the normal decay current is 24.5 m a, the normal attack current is 416.5 m a, and the fast attack current is 3.5 m a. the fast recovery mode decay current is 196 m a and the fast recovery mode attack current is 1.74 m a. the above mentioned attack and decay currents are not scaled with the data rate setting. after the data synchronizer pll is locked (sfc), the agc loop is switched to include the agc amplifier with a sampled charge pump, the programmable continuous time filter, full wave rectifier, and the sampling 5-tap equalizer to more accurately control the signal amplitude into the viterbi qualifier. in this sampled agc mode, a symmetrical attack and decay charge pump is used. the "1" sample amplitudes are sampled and held and compared to the ideal "1" value of 500 mv to generate the error current. the maximum charge pump current value can be programmed from the sample loop control register to 0, 34, 68, or 102 m a for maximum data rate and will scale downward with reduced data rate register values. agc control modes the agc control mode is determined by the state of bit 6 (agcsel) of the control operating register #1. if this bit is 0, then the direct, external agc control method is selected, i.e., agc uses external signals provided to the fastrec, lowz, and hold input pins. if bit 6 is a 1, the timed agc control method is selected for generating the internal hold, fast recovery, squelch, and low-z signals. d irect agc c ontrol m ode for maximum application flexibility, all agc mode control inputs are to be externally provided. when the lowz input is high, low-z mode is activated. in the low-z mode, the agc amplifier input resistance is reduced to allow quick recovery of the agc amplifier input ac coupling capacitors. the ratio of low-z to non low-z resistance can be selected as either 15:1 or 5:1 by programming the lztc bit in the data boost register. during low-z mode, the time constant of the internal ac coupling networks at the filter outputs are also reduced by the ratio determined by the lztc bit. this time constant is 300 ns in low-z and either 5 m s or 1.5 m s when not in low-z mode, depending on the state of the lztc bit. low-z also forces the agc amplifier gain to be reduced to near 0 v/v. this mode should be activated during and for a short time after a write operation. it should also be activated for a short time after each transition of the sg input and on initial power up. when the hold input is low, the charge pumps are disabled. this de-activates the agc loop. the agc amplifier gain will be held constant at a level set by the voltage at the byp or byps pins. the value of the capacitor placed at these pins should be selected to give adequate droop performance when in hold mode as well as to insure stability of the agc loop when it is active. the signal provided to the fastrec input pin determines if the agc is in fast recovery mode. during the fast recovery (fastrec=1), the attack and decay currents are increased to allow faster recovery to the proper agc level. if faster recovery than is provided by fastrec alone is desired, an ultra fast recovery can be effected by connecting a resistor between the agcrst pin and the positive supply vpa. if this resistor is present, whenever fastrec is entered, the voltage on the byp or byps capacitor will be pulled up. this causes an extremely rapid increase in the agc amplifier gain. the ultra fast current will be disabled the first time that the signal at dp/dn reaches the 125% point. the fastrec attack and decay currents are used as long as the fastrec pin is held high. t imed agc c ontrol mode this timed agc control mode differs from the direct control mode in that the external control inputs lowz, fastrec, and hold, are typically not used, and therefore, must be deasserted. the equivalent signals are generated internal to the P32P4910a. these internal signals are generated by one-shots that are triggered by various conditions of the wg/ wg, sg, and pdwn inputs. the one-shot timings for the low-z and fastrec signals are set by the resistors connected to the wrdel and agcdel input pins, respectively and analog ground. the time low-z period = 0.1 m s * r wrdel (k w ) and the fast recovery period = 0.1 m s * r agcdel (k w ) . the current for the ultra fast decay mode is set by the resistor connected between the agcrst input pin and vpa. in the timed mode, the agc shall use the c byp and c byps for non-servo and servo modes respectively. the nominal and fast attack and decay currents are the same in
1996 may 29 8 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a both of the P32P4910a's agc control modes. in internally timed mode, the lowz, fastrec, and hold input pins are logically or'ed with their respective internal control signals but do not affect the internal sequencing of the one-shot generated agc control signals. figure 1: agc timing (internal) diagrams - power-on mode pdwn agc input agc lowz fast filter offset recovery agc hold agc squelch agc fast recovery (attack & decay) agc ultra fast recovery (decay) t lz power-on gain recovery agc output 100% 125% normal attack + - ultra fast decay t lz t lz t fr t lz powered up fast attack ultra fast decay current is disabled when signal is greater than 125% of nominal.
1996 may 29 9 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a figure 2: agc timing diagrams - servo mode servo mode gain recovery sg agc input agc output 100% 125% ultra fast decay + - agc lowz fast filter offset recovery agc hold squelch agc fast recovery (attack & decay) agc ultra fast recovery (decay) t lz t fr t lz t lz fast attack t fr ultra fast decay current is disabled when signal is greater than 125% of nominal.
1996 may 29 10 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a figure 3: agc timing diagrams - write mode write mode gain recovery sg agc input agc output 100% 125% ultra fast decay normal attack + - agc lowz fast filter agc hold agc squelch agc fast recovery offset recovery agc ultra fast recovery t lz t lz (attack & decay) (decay) fast attack t fr ultra fast decay current is disabled when signal is greater than 125% of nominal.
1996 may 29 11 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a pulse quali?cation circuit descriptions this device utilizes three different types of pulse qualification, one exclusively for servo reads, one primarily for servo reads, and the other for data reads. s ervo r ead m ode for servo gray code reads, either a dual level (window type) qualifier or a hysteresis type level qualifier may be selected. if the pdm bit in the filter cutoff servo register is set to 0, then the window qualifier is selected, and if the pdm bit is a 1, the hysteresis qualifier is selected. the polarity of the rds/ rds is selected by the sms bit (servo mode select) in the data rate register. if sms=0 then rds is active-low and if sms=1 then rds is active-high. d ual l evel (w indow )q ualifier during servo reads (sg high) a dual level type of pulse qualifier is used. the level qualification thresholds are set by a 6-bit dac which is controlled by the servo level threshold register (lds). the register value is relative to the peak voltage at the output of the continuous time filter, derived off of the same reference voltage internal to the chip. the positive and negative thresholds are equal in magnitude. the state of the adaptive threshold level enable (ale) bit in the wp/lt register does not affect this dac's reference. the rds/ rds and the ppol outputs of the level qualifier indicate a qualified servo pulse and the polarity of the pulse, respectively. the rds/ rds and ppol outputs are only active when the sg input is high. h ysteresis q ualifier the hysteresis qualifier performs the same as the window qualifier except that the hysteresis qualifier guarantees that the second of two consecutive pulses of the same polarity will not be qualified. the hysteresis qualifier will only qualify pulses of alternating polarity. d ata r ead m ode in data read mode (rg high), the dual level qualifier used for servo reads, is used during vco sync field counting. its qualification thresholds are set by a 6-bit dac which is controlled by or the data level threshold register (ld). the register value is relative to the peak voltage at output of the continuous time filter and the dac both referenced to band gap voltage. the positive and negative thresholds are equal in magnitude. the state of the adaptive threshold level enable (ale) bit in the wp/lt register does not affect the dac's reference until the sync field count has been achieved. the rds/ rds and the ppol outputs of the level qualifier are not active in data read mode. v iterbi q ualifier the second type of pulse qualification, the viterbi qualifier, is only used during data read mode after the sync field count has been achieved. the viterbi qualifier has two significant blocks, one that feeds the other. the first block is the sampled pulse detector and the second is the survival sequence register. the sampled pulse detector performs the pulse acquisition/detection in the sampled domain. it acquires pulses by comparing the code clock sampled analog waveform to the positive and negative thresholds established by the programmable viterbi threshold window. the threshold window is defined to be the difference between the positive and negative threshold levels. the threshold window, vth, is set by a 7-bit dac which is controlled by the viterbi detector threshold register (vdt). while the window size is fixed by the programmed vth value, the actual positive and negative thresholds track the most positive and the most negative samples of the equalized input signal. for example, the viterbi positive signal threshold, vpt = vpeak (+) max if the previous detected level was (+). if the previous detect level was (-), vpt = vpeak(-)max + vth, where vpeak(-)max is the maximum amplitude of the previously detected negative signal. normally vth is set to equal vpeak (approx. 500 mv). after the pulses have been detected they must be further qualified by the survival sequence registers and associated logic. this logic guarantees that for sequential pulses of the same polarity within the maximum run length, only the latest is qualified. in this way, only the pulse of greatest amplitude will be qualified.
1996 may 29 12 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a the viterbi qualifier is implemented as two parallel qualifiers that operate on interleaved samples. each qualifier has a survival sequence register length of 5. to facilitate media scan testing, the viterbi survival sequence register may be bypassed by setting the bypsr bit in the viterbi detector threshold (vdt) register. programmable filter circuit description the on-chip, continuous time, low pass filter has register programmable cutoff and boost settings, and provides both normal and differentiated outputs. it is a 7th order filter that provides a 0.05 phase equiripple response. the group delay is relatively constant up to twice the cutoff frequency. for pulse slimming two zero programmable boost equalization is provided with no degradation to the group delay performance. the differentiated output is created by a single-pole, single-zero differentiator. both the boost and the filter cutoff frequency for data reads and the filter cutoff frequency for servo reads are programmed through internal 7-bit dacs, which are accessed via the serial port logic. the nominal boost range at the cutoff frequency is 0 to 13 db for data reads and is controlled by the data boost register. in servo mode, the boost can be programmed in 2 db steps from 0 to 6 db by programming the two fbs bits (bits 6 and 7) in the filter boost servo register. the cutoff frequency, ?c is variable from 4 to 34 mhz and controlled by the data cutoff register or servo cutoff register in the servo mode. the cutoff and boost values for servo reads are automatically switched when servo mode is entered. the filter zero locations can be programmed asymmetrically about zero to compensate for mr head time asymmetry. the asymmetry is adjusted by programming the 6 fgd bits (bits 0-5) in the filter boost servo register. the asymmetric zeros are not usable while in servo mode. the normal low pass filter is of a seven-pole two-real-zero type. figure 5 illustrates the transfer function normalized to 1 rad/s. the response can be denormalized to the cutoff frequency of | c (hz) by replacing s by s/2 p ?c, while the boost and group delay equalization are controlled by varying the a and b . figure 4: viterbi detection viterbi threshold window viterbi detector output + pulse detect - pulse detect for sequential pulses of the same polarity, the latest is selected by the survival sequence register logic since it is always of greater magnitude. +th -th
1996 may 29 13 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a with a zero at the origin, the filter provides a time-differentiated filter output. this is used in time qualification of the peak detection. to ease the timing requirement in peak detection of a signal slightly above the qualification threshold, the time-differentiated output is purposely delayed by 1.2 ns relative to the normal low pass output. the normal low pass output feeds the data qualifier (dp/dn), and the differentiated output feeds the clock comparator (cp/cn). five definitions are introduced for the programmable filter control discussion (figure 6): cutoff frequency: the cutoff frequency is the -3 db low pass bandwidth with no boost and group delay equalization, i.e. a =0 and b =0. actual boost: the amount of peaking in magnitude response at the cutoff frequency due to a1 0 and/or b1 0. alpha boost: the amount of peaking in magnitude response at the cutoff frequency due to a1 0 and without group delay equalization. in general, the actual boost with group delay equalization is higher than the alpha boost. however, with >3 db alpha boost, the difference is minimal. group delay d %: the group delay d % is the percentage change in absolute group delay at dc with respect to that without equalization applied ( b =0). group delay variation: the group delay variation is the change in group delay from dc to the cutoff frequency. this can be expressed as a percentage defined as: (change in group delay ? absolute group delay with b =0) * 100%. an alternative is to express the group delay variation in nanoseconds. because the absolute group delay variation in nanoseconds is scaled by the programmed cutoff frequency, the percentage expression is used in this specification. sm00010 in s 2 s+1.31703 s 2 +1.68495s+1.31703 2.95139 s 2 +1.54203s+2.95139 5.37034 s 2 +1.14558s+5.37034 0.86133 s+0.86133 s s+0.86133 normal differential figure 5: programmable filter normalized transfer function
1996 may 29 14 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a figure 6: filter magnitude response frequency (mhz) magnitude (db) sm00011 15 10 5 0 5 10 15 20 1 10 100 cutoff = 10mhz (i) 0db alpha boost & 0% group delay change (ii) 13db alpha boost & +30% group delay change 3db cutoff frequency actual boost, same as alpha boost with 0% group delay change or alpha boost is large actual 3db bandwidth with boost & group delay equalization (i) (ii)
1996 may 29 15 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a f ilter o peration direct coupled differential signals from the agc amplifier output are applied to the filter. the programmable bandwidth and equalization characteristics of the filter are controlled by 3 internal dacs. the registers for these dacs (fc, fb, and fgd) are programmed through the serial port. the current reference for the dacs is set using a single external resistor connected from pin vrx to ground. the voltage at pin vrx is proportional to absolute temperature (ptat), hence the current for the dacs is a ptat reference current. this establishes the excellent temperature stability for the filter characteristics. the cutoff frequency can be set independently in the servo mode and the data mode. in the data mode, the cutoff frequency is controlled by the data cutoff register. in the servo mode, the cutoff frequency is controlled by the servo cutoff register. c utoff c ontrol the programmable cutoff frequency from 4 to 34 mhz is set by the 7-bit linear fc dac. the fc register holds the 7-bit dac control value. the cutoff frequency is set as: ?c (mhz) = 0.301 * fc - 1.142 44 fc 117 for servo zones ?c (mhz) = 0.277 * fcs + 0.08 14 fcs 43 the filter cutoff (?c) is defined as the -3 db bandwidth with no boost applied. when boost/equalization is applied, the actual -3 db point will move out. the ratio of the actual -3 db bandwidth to the programmed cutoff is tabulated in table 1 as a function of applied boost and group delay equalization. figure 7: filter group delay response frequency (mhz) absolute group delay (ns) sm00012 70 1 10 100 cutoff = 0mhz (i) 0db alpha boost & 0% group delay change (ii) 13db alpha boost & +30% group delay change dc group delay change programmable from 30% to +30% (i) (ii) 1 65 60 55 50 45 40 group delay variation from `dc' to cutoff frequency
1996 may 29 16 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a b oost c ontrol the programmable alpha boost from 0 to 13 db is set by the 7-bit linear fb dac in data mode or 2-bit linear fbs dac in servo mode. the fb register holds the 7-bit dac control value and the fbs register holds the 2-bit control value. the alpha boost in data mode is set as: alpha boost (db) = 20 log [0.021848 * fb + 0.000046 * fc * fb + 1] 0 fb 127 the alpha boost in servo mode is set as: alpha boost (db) = 2 * fbs 0 fbs 3 that is, the boost in servo mode can be changed in 2 db steps from 0 to 6 db. the programmed alpha boost is the magnitude gain at the cutoff frequency with no group delay equalization. when finite group delay equalization is applied, the actual boost is higher than the programmed alpha boost. however, the difference becomes negligible when the programmed alpha boost is >3 db. table 2 tabulates the actual boost as a function of the applied alpha boost and group delay equalization. table 1: ratio of actual -3db bandwidth to cutoff frequency alpha boost group delay % 30% 25% 20% 15% 10% 5% 0% 0 db 1.62 1.47 1.31 1.16 1.06 1.01 1.00 1 1.74 1.62 1.50 1.38 1.28 1.21 1.19 2 1.87 1.79 1.71 1.63 1.56 1.51 1.49 3 2.01 1.96 1.91 1.87 1.83 1.80 1.79 4 2.14 2.11 2.09 2.07 2.05 2.04 2.03 5 2.25 2.24 2.23 2.22 2.21 2.20 2.20 6 2.35 2.34 2.34 2.33 2.33 2.32 2.32 7 2.44 2.44 2.43 2.43 2.42 2.42 2.42 8 2.52 2.52 2.51 2.51 2.51 2.51 2.51 9 2.59 2.59 2.59 2.59 2.59 2.59 2.59 10 2.67 2.66 2.66 2.66 2.66 2.66 2.66 11 2.73 2.73 2.73 2.73 2.73 2.73 2.73 12 2.80 2.80 2.80 2.80 2.80 2.80 2.80 13 2.87 2.87 2.86 2.86 2.86 2.86 2.86
1996 may 29 17 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a g roup d elay e qualization the group delay d % can be programmed between -30% to +30% by the 6-bit linear fgd dac. the fgd register holds the 6-bit dac control value. the group delay d % is set as: group delay d % = 0.9783 * (fgd4:0) - 0.665 0 fgd4:0 31 and fgd5 = sign bit the group delay d % is defined to be the percentage change of the absolute group delay due to equalization from the absolute group delay without equalization at dc. the current reference for the filter dacs is set using a single 12.1 k w resistor, from the vrx pin to ground. the voltage at vrx is proportional-to-absolute-temperature (ptat). the outputs of the filter are internally ac coupled to the qualifier inputs and buffers for the filter monitoring test points tpc+/tpc- and tpd+/tpd-. internal ac coupling the conventional external ac coupling at the filter to qualifier interface has been replaced by a pair of feedback circuits, one for the normal and one for the differentiated outputs of the filter. the offset of the filter outputs are sensed, integrat ed, and fed back to the filter output stage. the feedback loop forces the filter offset nominally to zero. in the normal read mode, (lowz=0), the integration time constant is set to 5 m s until the sync field counter reaches the programmed sfc count. at the sfc count, the offset sensing is switched into sampled mode and the time constant is reduces to 300 ns. in sampled mode the offset correction voltage is generated from the zeros qualified by the quantizer. this ensures that the sampled voltage level, not dp/dn, will be offset free. table 2: ratio of actual -3db bandwidth to cutoff frequency alpha boost group delays d % 30% 25% 20% 15% 10% 5% 0% 0 db 2.81 2.12 1.47 .89 0.42 0.11 0.00 1 3.36 2.76 2.21 1.72 1.33 1.09 1.00 2 3.97 3.45 2.99 2.58 2.27 2.07 2.00 3 4.66 4.19 3.80 3.47 3.21 3.05 3.00 4 5.34 4.97 4.65 4.38 4.17 4.04 4.00 5 6.10 5.79 5.52 5.30 5.14 5.03 5.00 6 6.89 6.64 6.42 6.24 6.11 6.03 6.00 7 7.72 7.51 7.34 7.19 7.09 7.02 7.00 8 8.58 8.41 8.27 8.15 8.07 8.02 8.00 9 9.47 9.33 9.22 9.12 9.05 9.01 9.00 10 10.4 10.3 10.2 10.1 10.1 10.0 10.0 11 11.3 11.2 11.1 11.1 11.0 11.0 11.0 12 12.2 12.2 12.1 12.1 12.0 12.0 12.0 13 13.2 13.1 13.1 13.1 13.0 13.0 13.0
1996 may 29 18 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a amplitude asymmetry detection and correction in the presence of amplitude asymmetry, such as that generated by mr heads, the sampled data processor (sdp) will be presented with zeros generated in one of two ways. the first is due the lack of a magnetic transition and will be referred to as a "real" zero. the second is produced by the superposition of adjacent +1 and -1 magnetic transitions and results in zero samples that shall be referred to as "cancelled" zeros. in the presence of amplitude asymmetry from an mr head, the "real" zeros are zero, but the "cancelled" zeros are offset by the difference between the +1 and -1 samples. the offset correction circuit forces the ground reference of the sampled data processor to the center of the "real" and "cancelled" zero sample levels. the integration time constant is increased by a factor of 4 to 1.0 m s, after the sync byte has been detected. a mplitude a symmetry m onitor p oint an amplitude asymmetry quality factor "qasym" may be selected to be output on the ato output pin by programming the asel bits in the power down register. this signal is derived by computing the average distance of the "real" and "canceled" zeros from the sampled data processor's system ground which was established between the two zeros levels by the offset correction circuit. the average distance is a measure of the asymmetry present in the mr read back signal. a gain of 4 from the sampled values is utilized and is low pass filtered with a time constant that is programmable to one of four different values by programming the two qtc bits in the control operating mode register #2. the signal is then buffered and differentially multiplexed to the ato pin. the signal is referenced to maxref/2. the asymmetry quality factor can be held at the value present at sync byte detect by setting the frezq bit in the wp/lt register. the value will be held for 10 ms and is not reset. the ato output may also be externally filtered to provide time constants that are appropriate for averaging over major portions of, or an entire sector. the capacitors on externally added filters must be externally reset. note that any external filtering added to ato output pin will affect both the amplitude asymmetry monitor signal and the equalization quality monitor signal since they are both muxed to the ato output pin. adaptive equalizer circuit description up to 7 db of equalization for fine shaping of the incoming read signal to the pr4 waveshape is provided by a 5 tap, sampled analog, transversal filter. this filter provides a self adaptive multiplier coefficient for the inner taps and a programmable coefficient for the outer taps. both inner taps use the same coefficient (km 1 ), and both outer taps use the same coefficient (km 2 ). for the adaptive inner taps, the value of km 1 is adjusted to force "zero" samples to zero volts. a special equalizer training pattern, located after the vco sync field in the sector format, is used to provide an optimum signal for the equalizer to adapt to. the adaptive property of these taps is enabled or disabled by the aee bit in the sample loop register. if the adaptive property is enabled, whether adaptation occurs only during the training pattern or both during the training pattern and the user data is controlled by the aed bit in the sample loop register. the adaptation can be observed when the equalizer control voltage is selected as the tpa+/tpa- output. the equalizer control voltage is approximately related to km1 by: km1 = 0.009 * date rate (mbit/s) * (tpa+ - tpa-) the multiplier coefficients for the adaptive taps can be held for up to 10 ms if the eqhold input is brought high after sync byte detect has occurred during a previous read in which proper training has occurred. the eqhold input pin may be asserted at any time during a read cycle and the adaptive coefficient km1 present at that time will be held, provided no leakage occurs, until the eqhold input is de-asserted. the multiplier coefficient, km 2, for the outer taps is programmable between +0.117 and -0.135 by the 4 km bits (bits 4-7) in the control operating mode register #2 .
1996 may 29 19 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a e qualization q uality m onitor p oint an equalization quality factor "q" may be selected to be output on the ato output pin by programming the atosel bits in the power down register and should be used as a guide for selection of the appropriate value for km 2. this signal is derived by computing the absolute distance of the "real" and "canceled" zeros from the sampled data processor's system ground which was established between the two zeros levels by the offset correction circuit. then the asymmetry factor (qasym) is subtracted and the resulting signal is full wave rectified and low pass filtered using one of the four time constants that may be programmed with the two qtc bits in the control operating mode register #2. the signal is then buffered and differentially multiplexed to the ato pin. the overall gain to the ato pin is 4. the signal is referenced to maxref/2. the equalization quality factor can be held at the value present at sync byte detect by setting the frezq bit in the wp/lt register. the value will be held for approx. 10 ms and is not reset . the ato output may also be externally filtered to provide time constants that are appropriate for averaging over major portions of, or an entire sector. the capacitors on externally added filters must be externally reset. time base generator circuit description the time base generator (tbg) is a pll based circuit, that provides a programmable reference frequency to the data separator for constant density recording applications. this time base generator output frequency can be programmed with a less than 1% accuracy via the m, n and dr registers. the tbg output frequency, fout, should be programmed as close as possible to ((9/8) * nrz data rate). the time base also supplies the timing reference for write precompensation so that the precompensation tracks the reference time base period. the time base generator requires an external passive loop filter to control its pll locking characteristics. this filter is fully-differential and balanced in order to reduce the effects of common mode noise. in read, write and idle modes, the programmable time base generator is used to provide a stable reference frequency for the data separator. in the write and idle modes, the time base generator output, when selected by the control test mode register, can be monitored at the tpb+ and tpb- test pins. in the read mode, the tbg output should not be selected for output on the test pins so that the possibility of jitter in the data separator pll is minimized. figure 8: block diagram of 5-tap equalizer y n = k m2 x n + k m1 x n-1 + x n-2 + k m1 x n-3 + k m2 x n-4 need more boost decrease km need less boost increase km +1 +1 +1 +1 0 0 0v 0v d d d d x n x n-1 x n-2 x n-3 x n-4 k m2 k m1 k m1 k m2 y n k m1 coefficient adapts to force '0' samples to 0v sm00026
1996 may 29 20 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a the reference frequency is programmed using the m and n registers of the time base generator via the serial port, and is related to the external reference clock input, fref, as follows: f tbg = fref * [(m + 1) ? (n + 1)] the m and n values should be chosen with the consideration of phase detector update rate and the external passive loop filter design. the data rate register must be set to the correct vco center frequency. the time base generator pll responds to any changes to the m and n registers, only after the dr register is updated. the dr register value, directly affects the following: center frequency of the time base generator vco, center frequency of the data separator vco, phase detector gain of the time base generator phase detector, phase detector gain of the data separator phase detector, write precompensation the reference current for the dr dac is set by an external resistor, rr, connected between the rr pin and ground. rr = 10.0 k w for 42 to 125 mbit/s data rate range rr = 12.1 k w for 33 to 100 mbit/s data rate range data separator circuit description the data separator circuit provides complete encoding, decoding, and synchronization for 8,9 (0,4,4) gcr data. in data read mode, the circuit performs clock recovery, code word synchronization, decoding, sync byte detection, descrambling, and nrz interface conversion. in the write mode, the circuit generates the vco sync field, scrambles and converts the nrz data into 8,9 (0,4,4) gcr format, precodes the data, and performs write precompensation. the circuit consists of five major functional blocks; the data synchronizer, 8,9 endec, nrz scrambler/descrambler, nrz interface, and write precompensation. d ata s ynchronizer the data synchronizer uses a fully integrated, fast acquisition, pll to recover the code rate clock from the incoming read data. to achieve fast acquisition, the data synchronizer pll uses two separate phase detectors to drive the loop. a decision-directed phase detector is used in the read mode and phase-frequency detector is used in the idle, servo, and write modes. figure 9: data synchronizer phase locked loop a vco charge pump read mode idle/write mode kds kdi gm m cint 12pf cext kvco sampled read data from adaptive equalizer reference frequency from time base generator vco ds clk sampled data phase detector phase/frequency detector
1996 may 29 21 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a in the read mode the decision-directed timing recovery updates the pll by comparing amplitudes of adjacent "one" samples or comparing the "zero" sample magnitude to ground for the entire sample period. a special (non ibm) algorithm is used to prevent "hang up" during the acquisition phase. the determination of whether a sample is a "one" or a "zero" is performed by a dedicated, dual mode, threshold comparator. this comparator's threshold levels are determined by the value, lth, programmed in the data threshold register. the fixed level threshold before the sync field count (sfc) has been achieved will be 1.4 times the threshold level after sfc since this is the ratio of the peak signal to the sampled "1" signal amplitude for pr4. the dual mode nature of this comparator allows the selection of either symmetric fixed or independent self adapting (+) and (-) thresholds by programming the adaptive level enable (ale) bit in the wp/lt register. also at sfc, the gain of the phase detector is reduced by a factor of 6 or 10, selectable by the gs bit in the damping ratio control register. this gain shift increases the loop's noise immunity during data tracking by reducing its bandwidth. the adaptive reference allows the specification of the threshold value to be a percentage of an averaged peak value. when adaptive mode is selected, the fixed thresholds are used until the sync field count (sfc) has been reached, then the adaptive levels are internally enabled. the time constant of a single pole filter that controls the rate of adaptation, is programmable by bits tc2-1 in the wp/lt register. in the write and idle modes the non-harmonic phase-frequency detector is continuously enabled, thus maintaining both phase and frequency lock to the time base generator's vco output signal, f tbg . the polarity and width of the detector's output current pulses correspond to the direction and magnitude of the phase error. the two phase detectors' outputs are muxed into a single differential charge pump which drives the loop filter directly. the loop filter requires an external capacitor. the loop damping ratio is programmed by bits 6-0 in the damping ratio control register. the programmed damping ratio is independent of data rate. in write mode, the tbg output is used to clock the encoder, precoder, and write precompensation circuits. the output of the precompensation circuit is then fed to the write data flip-flop which generates the write data (wd, wd) outputs. endec the endec implements an 8,9 (0,4,4) group coded recording (gcr) algorithm. the code has a minimum of no zeros between ones and a maximum of four zeros between ones for the interleaved samples. during write operations the encoder portion of the endec converts 8-bit parallel, scrambled or nonscrambled, data to 9-bit parallel code words that are then converted to serial format. in data read operation, after the code word boundary has been detected in the viterbi qualified serial data stream, the data is converted to 9-bit parallel form and the decoder portion of the endec converts the 9-bit code words to 8-bit nrz format. s ync b yte d etection the P32P4910a supports two types of sync byte detection, dual byte and single byte. d ual s ync b yte d etection the P32P4910a implements a dual "or" type sync byte detection scheme to reduce the probability that a single bit error will lead to the inability to synchronize. the two sync bytes are different and are spaced apart by one byte. the first sync byte is 1fh and the second is 69h. sync byte detection is considered to have occurred if either of the two sync bytes is found but the sync byte detect output pin ( sbd) is transitioned at the position in time when the second sync byte (69) would have been detected. the data placed on the nrz outputs when sbd goes low is always the second sync byte (69) regardless of which of the two was actually detected. s ingle s ync b yte d etection since the P32P4910a looks for either of the two sync bytes, the absence of the first sync byte is not an error. this allows for only a single byte to be written and still be able to achieve synchronization. it is recommended that only the 69h be written if single sync byte detection is desired so that when detection occurs, the data output on the nrz pins at sync byte detect will match the sync byte written.
1996 may 29 22 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a s ingle s ync b yte d etection when s emi a utomatic t raining i s e nabled when the autotr bit is set in the control operating register, the training/sync byte sequence is generated with an internal state machine. the internal state machine generates the 5-byte equalizer training pattern (93h) followed by the second sync byte (69h); the first sync byte (1fh) is not written by the internal state machine. to initiate the writing of the training pattern and sync byte in this mode, an ffh must be placed on the nrz bus for 6 byte times prior to the user data. this mode may be desirable if controller state machine space is very limited. s crambler /d escrambler the scrambler/descrambler circuit is provided to reduce fixed pattern effects on the channel's performance. it is enabled or disabled by bit 2 (sd) of the control operating register. in write mode, if enabled, the circuit scrambles the 8-bit internal nrz data before passing it to the encoder. only user data, i.e., the nrz data following the second sync byte (69h), is scrambled. in data read mode, only the decoded nrz data after the second sync byte (69h) is descrambled. the scrambler polynomial is h(x)= 1 ? x7 ? x10. the scrambler block diagram is shown in figure 10. the scrambler contributes no delay in either the encode or decode paths and therefore there is no difference in path delays whether or not the scrambler is enabled. nrz i nterface the nrz interface circuit provides the ability to interface with either a nibble or byte-wide controller. the nrz interface type is specified by the programming of bit 4 (nib) of the control operating register. if byte-wide mode is selected, the circuit does not reformat the data before passing it to and from the internal 8-bit bus. if nibble mode is selected, the nrz interface circuit converts the 4 lsbs of the external 8-bit bus to the internal 8-bit bus. only the selected nrz interface is enabled and the unused bits can be left floating. both the byte-wide and nibble interfaces define the most significant bit of the interface as the most significant bit of the data and the nibble interface defines the first nibble clocked in or ou t as the most significant of the pair. for both byte-wide and nibble operation, the nrz write data is latched by the P32P4910a on the rising edge of the wclk input. the wclk frequency must be appropriate for the data rate chosen or else overflow/underflow will occur. it is recommended that wclk be connected to rclk to prevent this from occurring. in byte-wide mode, as each nrz byte is input to the P32P4910a, its parity is checked against the controller supplied parity bit nrzp. if an error is detected, the perr output pin goes high and remains high until wg/ wg goes inactive. the timing is shown in figure 11. in data read mode, the nrz data will be presented to the controller near the falling edge of rclk so that it can be latched by the controller on the rising edge of rclk. when rg goes high, the selected nrz interface will output low data until the sync byte has been detected. the first non-zero data presented will be the sync byte (69h). the nrz interface is figure 10: P32P4910a scrambler block diagram x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xor nrz0-7 scram0-7 xor
1996 may 29 23 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a at a high impedance state when not in data read mode. in byte-wide mode, an even parity bit , nrzp, is generated for each output byte. w rite p recoder the P32P4910a implements a 1/(1 ? d 2 ) write precoder which is used to precode the serialized encoder data for pr4. the state of the precoder is preset to 0,0 upon exiting write mode. this guarantees that precoder will begin the next write in the 0,0 state. the state of the precoder is not guaranteed when the write data (wd/ wd) changes from sync field to encoded data. the result is that one of 2 different write data patterns or their inverses may be written for a particular write. all four of these patterns will decode properly upon read back. as a result of the fact that the write data toggle flip-flop is utilized as part of the precoder, the read/write amplifier connected to the P32P4910a must not contain a t flip-flop. the precoder block diagram is shown figure 12. figure 11: nrz timing rclk nrz0-7 read mode-byte wide byte 0 byte 1 wclk nrz0-7 write mode-byte wide byte 0 byte 1 rclk read mode-nibble nrz1 bit 5 bit 4 bit 0 nrz0 wclk nrz1 bit 5 bit 4 bit 0 write mode-nibble bit 4 nrz0 bit 7 bit 5 bit 3 bit 1 bit 7 nrz3 bit 6 bit 2 bit 6 nrz2 nrz3 bit 7 bit 5 bit 3 bit 1 bit 7 bit 6 bit 4 bit 2 bit 6 nrz2 byte 0 = msn byte 0 = lsn byte 1 = msn byte 0 = msn byte 0 = lsn byte 1 = msn figure 12: precoder block diagram d xor write current coded data d
1996 may 29 24 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a w rite p recompensation the write precompensation circuitry is provided to compensate for media bit shift caused by magnetic nonlinearities. the circuit recognizes specific write data patterns and can add delays in the time position of write data bits to counteract the magnetic nonlinearity effect. the magnitude of the time shift, wpc, is programmable via the write precomp register and is made proportional to the time base generator's vco period (i.e., data rate). the circuit performs write precompensation only on the second of two consecutive "ones" and only shifts in the late direction. if more than two consecutive "ones" are written, all but the first are precompensated in the late direction. servo demodulator circuit description servo functionality is provided by two separate circuits: the servo demodulator circuit, and the previously described dual level pulse qualifier circuit. to support embedded servo applications, P32P4910a provides separate programmable registers for servo mode filter cutoff frequency, boost, and qualification threshold. the values programmed in these registers are selected upon entry into servo mode (sg=1). either the normal or the differentiated filter output can be routed to the servo demodulator by programming the servo mode select (sms) bit in the data rate register. this bit also determines the polarity of the rds/ rds output. in addition, the rds/ rds pulse width and initial charge pump current is determined by the rdspw bit in the sample loop control register and the sbcc bits in the data level threshold register respectively. the servo demodulator circuit captures four separate servo bursts and provides an amplified and offset version of the voltages captured for each at the a, b, c, d output pins respectively. the circuit uses a "soft landing" charge pump with programmable initial charge current to charge each of the internal 10 pf burst hold capacitors. this "soft landing" charge pump architecture minimizes the overshoot of the hold capacitor beyond the actual instantaneous peak voltage at the full wave rectifier output. internal burst hold capacitors are provided to support low leakage burst capture and to reduce external component count. burst capture control is provided by the strobe and reset input pins. in addition to the a, b, c, d output pins, the circuit provides a maximum reference voltage at the maxref output pin. this reference voltage represents the maximum voltage that can be achieved at the a, b, c, d output pins with a 1.4 vpp signal at the filter output and is typically used as the reference voltage for an external a/d converter. b urst c apture burst capture is controlled by the signal applied to the strobe input pin and an internal counter. the first pulse on the strobe input pin causes the a burst hold capacitor to be charged by the charge pump. the capacitor charges for as long as the strobe input is high or until the capacitor voltage reaches the peak voltage at the full wave rectifier output. on the falling edge of the strobe signal, the internal counter is incremented. the next 3 strobe pulses will charge the b, c, and d, hold capacitors respectively. after the falling edge of the fourth strobe, the counter is reset to zero and the burst capture can be repeated. the counter is also reset when the reset input transitions low. the voltage level on each hold capacitor is amplified by a factor of 3.33 and summed with a 0.27v dc reference to create the a, b, c, and d output signals. a 1.40 vppd voltage at the dp/dn nodes will result in 1.40 * 0.6 * 3.33 = 2.80v peak burst amplitude (i.e., servo gain = 2.0). the maxref output pin is a nominal 3.2v and is internally divided by 12 to create the dc baseline of 0.27v. either the normal or differentiated filter output may be selected for full wave rectification for servo capture. if the servo mode select (sms) bit in the data rate register is 0 then the normal filter outputs are used and if it is a 1, the differentiated filter outputs are used. if the differentiated output is selected, the polarity of the rds/ rds pulse will be positive true otherwise rds/ rds is negative true. the magnitude of the captured voltage on the burst hold capacitors is governed by setting of the 2-bit servo agc dac. the agc voltage can be programmed from 1.10 to 1.40 vppd. all four of the internal hold capacitors are discharged when the reset input is driven low. the reset input overrides the strobe signal. strobe and reset are not gated with sg. the maximum charge pump current can be selected as 40, 80, 120 or 160 m a by setting the servo burst charge current (sbcc) bits in the data level threshold register. the "soft landing" technique reduces the charge pump current as the error between the voltage on the hold capacitor and the full wave rectifier output becomes smaller. this reduces the possibility of overcharging the capacitor during the comparator's propagation delay period.
1996 may 29 25 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a a small leakage current is applied to the capacitor being charged during each strobe period to make the captured voltage less sensitive to noise and strobe timing. the magnitude of this current is 1/450 of the charge current. servo data burst c burst b burst a sg strobe reset sm00025 burst d figure 13: servo capture timing diagram figure 14: servo burst acquisition (sg = reset = 1) strobe
1996 may 29 26 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a servo timing outputs the dual level qualifier that was previously described is used to generate the rds/ rds and ppol timing signals. the rds/ rds output pin pulses low for each positive or negative servo peak that is qualified by the dual level qualifier. the pulse width of rds/ rds may be selected as either 15 ns or 27 ns with the rdspw bit in the sample loop control register. the ppol output pin provides the pulse polarity information for the qualified peaks, where ppol=1 for a positive peak and ppol=0 for a negative peak. to reduce noise propagation, the rds/ rds and ppol outputs are only active in servo mode. serial port circuit description the serial port interface is used to program the P32P4910a's seventeen internal registers. the serial port is enabled for data transfer when the serial data enable (sden) pin is high ("1"). sden must be asserted high prior to any transmission and it should remain high until the completion of the transfer. at the end of each transfer sden should be brought low ("0"). when sden is high, the data presented to the serial data (sdata) pin will be latched into the P32P4910a on each rising edge of the serial clock (sclk). rising edges of sclk should only occur when the desired bit of address or data is being presented on the serial data line. serial data transmissions must occur in 16-bit packets. if more than 16 rising edges of sclk are received during the time that sden is high, only the last 16 are considered valid. for all valid transmissions, the data is latched into the internal register on the falling edge of sden. each 16-bit transmission consists of a read/write control bit (must always be reset, i.e., r/ w = "0" for write only) followed by 3 device select bits, 4 address bits and eight data bits. the device select and address bits select the internal register to be written to. the device select, address and data fields are input lsb first, msb last, where lsb is defined as bit 0. the three device select bits select the type of device on the philips semiconductors serial bus to be communicated with figure 15: rds/ rds and ppol vs. dp/dn relationship dp/dn + threshold - threshold rds ppol (+lsth) (-lsth)
1996 may 29 27 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a and must be set to s0 = 0 or 1 (depending on register to be selected), s1 = 1, and s2 = 0 when communicating with the P32P4910a. the figure below shows the serial interface timing diagram. description of operating modes the fundamental operating modes of the P32P4910a are controlled by the servo gate (sg), read gate (rg), and write gate (wg/ wg) input pins. the exclusive assertion of any these inputs causes the device to enter that mode. if none of these inputs is asserted, the device is in the idle mode. if more than one of the inputs is asserted, the mode is determined by the following hierarchy: sg overrides rg which overrides wg/ wg. the mode that is overriding takes effect immediately. rg and sg are asynchronous inputs and may be initiated or terminated at any position on the disk. wg/ wg is also an asynchronous input, but should not be terminated prior to the last output write data (wd/ wd) pulse. mode control i dle m ode o peration if sg, rg, and wg/ wg are not active, the P32P4910a is in idle mode. when in idle mode, the time base generator and the data separator pll are running and the data separator pll is phase-frequency locked to the tbg vco output. the agc, continuous time filter, and pulse qualifiers are active but the outputs of the pulse qualifiers are disabled. the continuous time filter is using its programmed values for cutoff frequency and boost determined by the data mode registers. the agc operation is the same as in the vco preamble portion of a data read. servo burst capture is operational in idle mode but the filter and agc settings are for data reads and not for servo reads as would be the case if the device was in servo mode. the rds/ rds and ppol outputs are disabled in idle mode. wg/ wg rg device mode description 0/1 0 idle mode ds vco locked to f tbg . nrz7-0 tri-stated. 0/1 1 data read mode ds pll acquisition, adaptive equalizer training, code word boundary search and detect, decode, sync byte detect, and nrz data output. ds vco switched from f tbg to rd after preamble detect. rclk gen. input switched from f tbg to ds vco. rclk re-synchronized to rd at code word boundary detect. nrz7-0 active. 1/0 0 data write mode write mode preamble insertion and data write. ds vco locked to f tbg . rclk synchronized to f tbg . wd and wd active. nrz7-0 = inputs. 1/0 1 read override rg overrides wg/ wg which causes any write in progress to cease and data read mode to be entered. figure 16: serial interface timing sden sclk sdata t c t sens t ckl t ckh t ds t dh t senh t sl complete register string id r/w a0o s0 s1 s2 a0 a3 d0 d7 sm00003
1996 may 29 28 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a s ervo m ode o peration if sg is high, the device is in the servo mode. this mode is the same as idle except that the filter cutoff and boost settings are switched from those programmed for data read mode to those programmed for servo mode, the agc is switched to servo mode, and the rds/ rds and ppol and outputs are enabled. the assertion of sg causes read mode, write mode, and the power down register settings for the front end to be overridden. w rite m ode o peration the P32P4910a supports three different write modes; normal write mode, direct write mode #1 and direct write mode #2. the direct write modes require that either the direct write bit, bit 0 of the control operating register, or the dwr pin be active. all three write modes require that the data separator be powered on. the active polarity of write gate can be selected by programming the wgp bit in the control operating register. the pdwn input should be kept low until all registers are properly loaded to prevent an illegal write operation at power up. n ormal w rite m ode the P32P4910a is in the normal write mode if wg/ wg is active, dwr is high, and the direct write bit in the control operating register is low. a minimum of one nrz time period must elapse after rg goes low before wg/ wg can be set active. the data separator pll is phase-frequency locked to the tbg vco output in this mode. in normal write mode, the circuit first autogenerates the vco sync pattern, then scrambles the incoming nrz data from the controller, encodes it into 8,9 gcr formatted data, precodes it, precompensates it, feeds it to a write data toggle flip-flop, and outputs it to the preamp for storage on the disk. when wg/ wg goes inactive, the wd/ wd outputs remain enabled but the active pull down current is reduced by a factor of 7 to reduce power consumption and the write data flip-flop is reset to guarantee that the wd/ wd outputs represent a zero state. in normal write operation, when the write gate (wg/ wg) goes active, the vco sync field generation begins, which causes a continuous "2t" pattern at the wd/ wd outputs {(1,1,-1,-1,1,1,-1,-1...) in the write current domain}. the nrz inputs must be low and must be held low for the duration of the vco sync field generation. the minimum required sync field is equivalent to 8 byte times. the P32P4910a also allows the precoder to be preset when the first training byte arrives at the precoder. with control operating mode register #2 bit 3 (tme) and bit 0 (pcfdis) set to 0, the P32P4910a allows presetting of the precoder. bit 2 (pfspol) of the control operating mode register #2 allows the precoder to be preset if pfspol is set to 1 and reset if set to 0. t raining and s ync b yte g eneration the P32P4910a supports two modes of sync byte detection, single byte and dual "or" byte, and two modes of training and sync byte generation, manual and semi-automatic. the manual mode is generally recommended because it can be used for either dual or single sync byte detection and provides more flexibility in altering the number of training bytes to be written. the semi-automatic mode can only be used to generate an internally fixed number of training bytes and a single sync byte, but saves controller state machine space. m anual m ode in the manual mode, the device will continue to autogenerate the sync field pattern until a 93h is latched at the nrz interface, and detected. the device encodes the 93h pattern and writes the result as the training pattern. for the single sync byte detection mode, a recommended minimum of 5 bytes of 93h must be written to the nrz interface to write the 5 byte equalizer training pattern. next, the nrz data must be changed to 69h for 1 byte time to write the single sync byte. for the dual sync byte detection mode, a recommended minimum of 4 bytes of 93h must be written to the nrz interface to write the minimum 4 byte equalizer training pattern. the nrz data must then be changed to 1fh for one byte time to write the first sync byte. the nrz data must then be changed to 93h for one byte time to write a training/propagation byte. next, the nrz data must be changed to 69h for one byte time to write the second sync byte.
1996 may 29 29 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a s emi -a utomatic m ode in the semi-automatic mode, the device will continue to autogenerate the sync field pattern until a ffh is latched at the nrz interface, and detected. the device then internally generates the encoded the 93h pattern for 5 byte times and writes the result as the training pattern. it then internally generates the encoded 69h pattern for 1 byte time to write the single sync byte. to maintain proper controller synchronization, the ffh should be presented at the nrz interface for a total of 6 byte times. note that the semi-automatic mode can only be used to write single sync byte format and the training pattern length is fixed at 5. this mode is useful if controller state machine space is extremely limited. u ser d ata the user data must be presented at the nrz interface immediately following the last nrz sync byte written. finally, after the last byte of user data has been clocked in, the wg/ wg must remain active for a minimum of 16 nrz bit times in byte-wide mode to ensure the that the device is flushed of data (the delay is 21 nrz bit times in nibble mode). wg/ wg can then go inactive. wd/ wd stops toggling a maximum of 2 nrz (rclk) time periods after wg/ wg goes inactive. d irect w rite m ode #1 in this direct write mode, the nrz data from the byte-wide interface bypasses the scrambler, the 8,9 encoder and the precoder, but is precompensated before going to the write data flip-flop and then to the wd/ wd output pins. the rclk output is changed from 9 vco clock periods to 8 vco clock periods with a 3/8 duty cycle. the purpose of routing the signal to the precomp circuit is to generate a return to zero pulse every time a "1" occurs in the data so that the write data flip-flop is toggled. wclk is not required to latch the byte-wide nrz data into the nrz interface since the data is latched by an internal version of rclk, but the nrz data must be valid no later than 12 ns after the rising edge of the rclk output pin. direct write mode #1 is selected by setting the dw bit (bit 0) in the control operating register. and is entered when the wg/ wg input is active. this mode is not valid when using the nibble nrz interface. note that direct write mode #2 will override direct write mode #1. figure 17: hard sector write sequence - dual sync gap 8 bytes min. 4 bytes min. 1 byte nrz data (write) 00h 93h 69h user data wg 1 byte 1fh 1 byte 93h vco sync field training sequence sync byte#1 train byte sync byte#2 scrambled and encoded user data figure 18: hard sector semi-auto write mode gap 8 bytes min. 5 bytes 1 byte nrz data (written to 4910a) 00h ffh ffh user data wg nrz data (written by 4910a) 00h 93h 69h user data vco sync field training sequence sync byte scrambled and encoded user data
1996 may 29 30 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a d irect w rite m ode #2 in this direct write mode, the data presented at the dwi/ dwi input pins directly toggles the write data flip-flop which drives the wd/ wd output pins. no wclk is required in this mode, and the wd/ wd output is not resynchronized. direct write mode #2 is selected by driving the dwr input low and is entered when the wg/ wg input is active. note that the direct write mode #2 will override direct write mode #1. d ata r ead m ode o peration data read mode is initiated by setting the read gate (rg) input pin high. this action causes the data synchronizer to begin acquisition of the clock from the incoming vco sync pattern. to achieve this, the data synchronizer utilizes a fully integrated fast acquisition pll to accurately develop the sample clock. this pll is normally locked to the time base generator output, but when the read gate input (rg) goes high, the pll's reference input is switched to the filtered incoming read signal. a cquisition of ds vco s ync when the read gate input is asserted, the read sequence is initiated. at this time an internal counter begins counting the pulses that are qualified by the dual level pulse qualifier given the polarity changes of the incoming 1,1,-1,-1,1,1 read back pattern defined by the vco sync field. when the count reaches 4, the internal read gate is asserted and the ds pll input is switched from the tbg's vco output to the sampled data input. this is also the point at which the ds pll's phase detector is switched from the phase-frequency detector to the decision directed phase detector. the counter is also used to determine whether the selected sync field count, sfc, has been achieved. when the counter reaches the value specified by sfc, the data synchronizer pll is assumed to be locked and settled (vco lock). also at sfc, the phase detector gain switch and the agc mode switch occur. to allow for different preamble lengths, the sfc can be set figure 19: read sequence - dual or single sync byte modes gap 8 bytes min. 5 bytes min. 1 byte nrz data high z 00h 00h 00h user data rg sbd 1 byte 69h 1 byte 00h sync byte#2 sync byte#1 train byte training sequence vco sync field scrambled and encoded user data figure 20: semi-auto sector read mode gap 8 bytes min. 5 bytes 1 byte nrz data 00h 00h ffh user data wg vco sync field training sequence sync byte scrambled and encoded user data sbg high z
1996 may 29 31 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a to 64, 80, 96 or 128 from the sample loop control register. these values for the sfc may be thought of as the number of code clock periods in the sync field, but they actually represent twice the number of incoming polarity changes required. vco l ock ,pdg ain , agc m ode s witch , and c ode w ord b oundary d etector e nable at sfc, one of two phase tracking methods will be chosen depending on the enable phase detector gain switching (gs) bit in the control operating mode register. when the gs bit is high, the phase detector gain is reduced by a factor of 6 or 10 as dictated by the gs_10 bit after the sfc count is reached. when the gs bit is low, no phase detector gain switching takes place. also after sfc, the agc feedback will be switched from the continuous time fullwave rectifier to sampled data feedback. at sfc, the internal vco lock signal activates the code word boundary detection circuitry to define the proper decode boundaries. also, at count sfc, the rclk generator source switches from the tbg's vco output to the ds vco clock signal which is phase locked to the incoming read data samples. the ds vco is assumed locked to the incoming read samples at this point. at sfc a maximum of 1 rclk time period may occur for the rclk transition, however, no short duration glitches will occur. after the code word detection circuitry finds the proper code word boundary, the rclk generator is again resynchronized to guarantee that the rclk is in sync with the data. the rclk output will not glitch and will not toggle during this rclk generator resynchronization for up to 2 byte times maximum. also at the code word boundary detect, the internal 9-bit code words are allowed to pass to the endec for decoding. this decoding will occur until read gate is deasserted. a daptive e qualizer t raining s equence t raining s equence for s ingle s ync b yte m ode as was previously discussed, in a single sync byte type write sequence, a minimum of 5 bytes of nrz 93h and one byte of 69h must be written between the end of the vco sync field and the beginning of the user data. the 5 bytes of 93h are 8,9 encoded and precoded during write mode to produce the adaptive equalizer training pattern. during read mode, the encoded 93h sequence (100110011 read data sequence) and the encoded 69h are used to adaptively train the inner two taps of the five tap transversal filter in a zero forcing manner. the error at the filter output is integrated to derive t he tap weight multiplying coefficient, km1. both of these inner taps use the same km1. it is anticipated that the continuous time filter will be used for coarse equalization and that transversal filter will be used adaptively for fine tuning. this wil l reduce kms range and accuracy requirements. since there are encoded user data patterns that will not produce an equalizer correction error, an equalization hold during data mode can be selected from the sample loop control register. if the equalizer is programmed to adapt only during the training sequence, the sync byte detect signal is used to hold the km1 value. after the training pattern, if the loop is active during user data, the equalizer loop gain will be reduced by 7. the loops integration time constant is made inversely proportional to the selected data rate. the km1 coefficient can be held at the present instantaneous value by asserting the eqhold input. if eqhold is asserted, the km1 value will not be changed by either exiting read mode, subsequent training patterns, or by subsequent data patterns. when eqhold is deasserted, the equalizer will resume its normally programmed functionality. the km1 value can be held with reasonable accuracy for up to 10 ms to make the number of code periods required for acquisition data rate independent. t raining s equence for d ual s ync b yte m ode the adaptive equalizer training used for the dual sync byte detection mode is the same as that used in the single sync byte mode except that the adaptation occurs over the 4 encoded 93h bytes, sync byte #1 (1fh), another 93h and sync byte #2 (69h). this occurs because the sync byte detect ( sbd) is what disables the adaptation if adaptation is enabled only during the training sequence. the number of consecutive 93h training bytes may be reduced in dual sync byte mode because the sync byte #1 has been chosen to have the same training properties as the 93h training byte.
1996 may 29 32 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a s ync b yte d etect and nrz o utput the P32P4910a implements a dual "or" type sync byte detection which offers increased sync byte detection capability while maintaining backward compatibility with the single sync byte format and detection. the two bytes of the dual sync byte are separated by a training byte to allow for viterbi error propagation that may be caused by an error in the first sync byte. the training byte 93h was chosen to provide the adaptive equalizer an ideal training signal. as the read data is 8,9 decoded, it is compared to one of two internally fixed sync bytes (1fh or 69h). if the 1fh byte is found, the sbd output will go low 18 code clocks (2 byte times) later and the 69h byte will be the first non-zero byte presented at the nrz interface. if a match of the 69h byte is the first found, the sync byte detect ( sbd) pin goes low and the nrz output data that until now was held low, is changed to 69h. the next byte presented on the nrz outputs is the first byte of user data. sbd will remain low and nrz data will continue to be presented at the nrz interface until the read gate is deasserted at which point sbd goes high and the nrz outputs go to a high impedance state. s urface d efect s can m ode the P32P4910a helps check for media defects using the surface defect scan mode. in order to use this mode the part must have the byte-wide interface enabled. in write mode, all zeros are presented (written) at the nrz interface. when this pattern is to be read back, bit 7 (dse bit) of the n counter register is enabled which enables the surface defect scan mode. the survival sequence register must also be turned off (bypsr bit). in this mode, sbd will transition low at sfc. the nrz7 pin is monitored. if no defect occurs, the nrz7 pin will stay low. if a defect occurs, the nrz7 pin will transition high on the falling edge of rclk and stay high as long as the defect is present, transition back low on the next falling edge of rclk when the defect is not present. power down operation the power management modes of the P32P4910a are determined by the states of the power down register bits and the pdwn and sg inputs. the individual sections of the chip can be powered down or up using the power down register. a high level in a power down register bit disables that section of the circuit. the power down information from the power down register takes effect immediately after the sden pin goes low. when the pdwn input is low, the chip goes into full power down mode regardless of the power down register settings or the state of the sg input. figure 21: surface defect scan mode sfc rg sbd rclk nrz7 defect sm00002
1996 may 29 33 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a when pdwn is high, sg will force the agc, filter, and pulse qualifier circuits (front end) to be active by overriding the front end register bit. the back end power down register bits, which include the data separator and time base generator are not affected by the sg input. the serial port is active in all power down modes. the time to restart from a full power down is dependent on the pll loop filter and the data rate. the truth table for the various modes of operation is shown below: sg, pdwn : 1,1 1,0 0,1 0,0 front end on off r off data separator r off r off time base generator r off r off serial port on on on on r = controlled by register bit. (register bit =1 turns circuits off, register bit = 0 turns circuits on)
1996 may 29 34 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a register descriptions serial port register de?nitions complete register string id a3 a2 a1 a0 s2 s1 s0 r/ w power down register (pd) 0 0 0 0 0 1 0 0 04h bits 7-6 tpc/d1-0 test point c/d control (tme = 0) tpc+/tpc- tpd+/tpd- tpe 0x = disabled disabled disabled 1x = dp/dn cp/cn disabled sg = 1 1x = disabled disabled disabled sg = 0 tpc /d1-0 test point c/d control (tme = 1) tpc+/tpc- tpd+/tpd- tpe (agcsel=0) tpe (agsel=1) 00* = servo mode calibration 01 = dp/dn cp/cn full wave low-z oneshot rectifier out as input mode to qualifiers, etc. 10 = dp/dn cp/cn full wave fastrec rectifier out oneshot output mode from filter/offset canceller 11 = filter filter full wave ultra fast bypass bypass rectifier out decay ctrl. bits 5-4 atosel output select for ato test point 00 = maxref/2 01 = dac output enabled dac test mode 10 = amplitude asymmetry monitor output (qasym) selected 11 = channel equalization monitor output (q) selected bit 3 accpl internal ac coupling enable/disable (tme = 0) 0 = internal ac coupling, agc switched to sample mode at sfc 1 = internal ac coupling, agc is always in continuous mode internal ac coupling enable/disable (tme = 1) 0 = internal ac coupling is enabled, agc as per tme = 0 state 1 = internal ac coupling is disabled bit 2 tb time base generator power down 0 = power up 1 = power down; bit 1 ds data separator power down 0 = power up 1 = power down; bit 0 pd agc, filter, pulse detector, and servo power down 0 = power up 1 = power down; * servo calibration mode enabled, strobing must occur for operation. data filter cutoff register (fc) 0 0 0 1 0 1 0 0 14h bit 7 3tapen 3 tap equalizer enable 0 = enable 5 tap equalizer (normal operation) 1 = enable only 3 tap equalizer (4901 mode) bits 6-0 fc6-0 filter cutoff frequency setting in non-servo mode ?c (mhz) = 0 . 301 * fc - 1.142 44 < fc < 117 dec
1996 may 29 35 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a servo filter cutoff register (fcs) 0 0 10010024h bit 7 pdm servo peak detector mode 0 = window quali?er 1 = hysteresis quali?er bits 6-0 fcs6-0 filter cutoff frequency setting in servo mode ?c (mhz) = 0 . 277 * fc + 0.08 14 < fc < 43 dec data filter boost register (fb) 0 0 1 1 0 1 0 0 34h bit 7 lztc non low-z vs. low-z time constant 0 = 15:1 1 = 5:1 bits 6-0 fb6-0 filter boost setting in data mode boost (db) = 20 * log[0.021848 * fb + 0.000046 * fb * fc + 1] 0 < fb < 127 dec servo filter boost register (fbs) 0 1 00010044h bits 7-6 fbs 1-0 filter boost setting in servo mode 00 = 0 db 01 = 2 db 10 = 4 db 11 = 6 db bits 5-0 fgd5-0 filter group delay d % in all modes group delay d % = 0.9783 * (fgd 4-0) - 0.665, where fgd5 = 1 is positive, 0 is negative 0 fgd 31 dec viterbi detector threshold register (vdt) 0 1 01010054h bit 7 bypsr survival sequence register bypass/write precode bypass 0 = bypass disabled (normal operation) 1 = bypass enabled bits 6-0 vd6-0 viterbi quali?cation threshold voltage vth (mv) = 7.874 * vd 45 vd 127 dec data level threshold register (ld) 0 1 10010064h bits 7-6 sbcc1-0 initial servo charge pump current 00 = 40 m a 01 = 80 m a 10 = 120 m a 11 = 160 m a bits 5-0 ld5-0 data level quali?cation threshold voltage if wp/lt register : ale = 0 (fixed levels) prior to sfc : lth (mv) = 10.47 * ld after sfc : lth (mv) = 7.44 * ld 16 ld 63 dec if wp/lt register : ale = 1 (adaptive levels) after sfc : lth (%) = 1.574 * ld serial port register de?nitions (continued) complete register string id a3 a2 a1 a0 s2 s1 s0 r/ w
1996 may 29 36 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a servo level threshold register (lds) 0 1 11010074h bits 7-6 sagc lvl1-0 servo mode agc level control 00 = 1.40 vppd 01 = 1.30 vppd 10 = 1.20 vppd 11 = 1.10 vppd bits 5-0 lds5-0 servo level quali?cation threshold voltage lsth (mv) = 10.47 * lds control test mode register (ct) 1 0 00010084h bit 7 efr sample clock source 0 = sample clock is from the ds vco, normal operation 1 = sample clock is from the tbg output, a test mode bit 6 ecp factory reserved bit, must be set to 0 in application (enables charge pump) bits 5-3 tp3-1 multiplexed test point selection tp3 tp2 tp1 function tpa+, tpa- tpb+, tpb- 0 0 0 test points off high impedance high impedance 0 0 1 survival out/in ssout a, b (sngl) ssin a+, a- (sngl), 0 1 0 eq cont/phase det equalizer control (diff) phase detect out (diff), 0 1 1 viterbi survival in ssin b+,b- (sngl) ssin a+, a- (sngl), 1 0 0 equalizer outputs equalizer a (diff) equalizer b (diff) 1 0 1 eq out/survival in equalizer a (diff) ssin a+, a- (sngl) 1 1 0 eq out/survival out equalizer a, b (sngl) ssout a, b (sngl) 1 1 1 eq out/vco/2 equalizer a, b (sngl) ds vco/2 (diff) for rg = 1 eq out/tbg out equalizer a, b (sngl) tbg out (diff) for rg = 0 serial port register de?nitions (continued) complete register string id a3 a2 a1 a0 s2 s1 s0 r/ w
1996 may 29 37 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a serial port register de?nitions (continued) complete register mode a3 a2 a1 a0 s2 s1 s0 r/ w control test mode register (ct) (continued) 1 0 00010084h bit 2 rck2x/ vrdt enable double rclk drive (tme = 0) at byte wide nrz interface 0 = rclk drive at 1x 1 = rclk drive at 2x enable vrdt input (tme = 1) 0 = viterbi survival outputs to the data decoder, normal use 1 = digital input to the data decoder, used in testing only bit 1 dt 0 = not in pump down test mode 1 = digital input to the data decoder, for test only bit 0 tt/ut training termination found sync byte (tme = 1) 0 = terminate training when sbd goes low 1 = terminate training 4 bytes after framing enable tbg pump up (tme = 1) 0 = not in pump up test mode 1 = continuous pump up, for test use only fltr1+ sources current; fltr1- sinks current n counter register (n) 1 0 0 1 010094 bit 7 dse defect scan enable 0 = normal operation 1 = defect scan mode enabled bits 6-0 n6-0 n counter 2 < n < 127 m counter register (m) 1 0 1 0 0100a4h bits 7-0 m7-0 m counter 2 < m < 255 f tbg = fref * [(m+1) ? (n+1)] data rate register (dr) 1 0 1 1 0100b4h bits 7 sms servo mode select 0 = capture uses normal ?lter output and rds is active low (normal operation) 1 = capture uses differentiated ?lter output and rds is active high bits 6-0 dr6-0 fvco (mhz) = 9/8 data rate = 1.143 * dr + 4.986 for rr = 10 k w fvco (mhz) = 9/8 data rate = 0.948 * dr + 1.831 for rr = 12.1 k w 37 < dr < 127
1996 may 29 38 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a serial port register de?nitions (continued) complete register id string a3 a2 a1 a0 s2 s1 s0 r/ w write precomp / level threshold time constant register (wplt) 1 1 000100c4h bits 7-6 tc2-1 adaptive level quali?cation threshold time constant for decision directed phase detector. (valid after sfc) tc2 0 0 1 1 tc1 0 1 0 1 t ime constant 200 ns 400 ns 600 ns 800 ns bit 5 ale enable adaptive level quali?cation in decision directed phase detector 0 = ?xed level quali?cation 1 = adaptive mode bit 4 frezq freeze channel quality factor and asymmetry factor at sync byte detect 0 = update during read 1 = freeze at sbd bits 3-0 wpc3-0 write precomp setting wpc3 wpc2 wpc1 wpc0 write precomp magnitude 0 0 0 0 no precomp 0 0 0 1 2.1% code period shift 0 0 1 0 4.2% code period shift 0 0 1 1 6.3% code period shift 0 1 0 0 8.4% code period shift 0 1 0 1 10.5% code period shift 0 1 1 0 12.6% code period shift 0 1 1 1 14.7% code period shift 1 0 0 0 16.8% code period shift 1 0 0 1 18.9% code period shift 1 0 1 0 21.0% code period shift 1 0 1 1 23.1% code period shift 1 1 0 0 25.0% code period shift 1 1 0 1 27.3% code period shift 1 1 1 0 29.4% code period shift 1 1 1 1 31.5% code period shift
1996 may 29 39 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a serial port register de?nitions (continued) complete register id string a3 a2 a1 a0 s2 s1 s0 r/ w control operating register (cm1) 1 1 010100d4h bit 7 autotr enables semi-automatic training and sync byte generation 0 = disabled (normal operation) 1 = enabled (single sync byte only) bit 6 agcsel selects agc control mode 0 = direct mode i.e., external control signals must be provided 1 = timed mode i.e., control provided by one shot timing from sg and wg/ wg bit 5 wgp write gate polarity 0 = active high, (normal operation) 1 = active low bit 4 nib enable nibble interface 0 = nibble interface disabled, i.e., byte-wide interface enabled 1 = nibble (nrz3-0) interface enabled bit 3 bt bypass time base generator 0 = data synchronizer reference frequency is tbg output, (normal operation) 1 = data synchronizer reference frequency is fref input bit 2 sd disable data scrambler/descrambler 0 = enabled, (normal operation) 1 = disabled bit 1 gs ds phase detector gain switching 0 = enabled, (normal operation) 1 = disabled bit 0 dw enable direct write from byte-wide nrz (bypasses scrambler and endec) 0 = disabled; (normal operation) 1 = enabled, sample loop control register (slc) 1 1 100100e4h bit 7 rdspw rds output pulse width 0 = 15 ns 1 = 27 ns bits 6-5 sfc1-0 sync field count sfc1 0 0 1 1 sfc0 0 1 0 1 sync field count (code clocks) 64 80 96 128
1996 may 29 40 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a bit 4 aegs adaptive equalizer loop time constant shift 0 = equalizer loop time constant same in preamble and data ?elds 1 = equalizer loop time constant is increased to 7x in the data ?eld elative to the preamble ?eld, i.e. loop gain is reduced to 1/7 bit 3 aed enable adaptive equalizer on data field 0 = adaptive equalizer disabled after preamble ?eld 1 = adaptive equalizer in use after preamble ?eld, if aee bit = 1 bit 2 aee enable adaptive equalizer 0 = adaptive equalizer disabled 1 = adaptive equalizer enabled for use in preamble ?eld, and after the preamble ?eld if aed bit = 1 bits 1-0 agc1-0 agc charge pump current in sampled agc mode agc charge/discharge current ( m a) = 2.66 * agc * dr/rr (k w ) 37 < dr < 127, rr = 10 k w e.g., for dr = 100 and agc=10 =2 dec charge pump current = 53 m a damping ratio control register (drc) 1 1 110100f4h bit 7 gs_10 data separator pll gain shift factor 0 = 6 1 = 10 bits 6-0 d6-0 damping ampli?er gain a = d * (0.8 / 127) damping ratio = serial port register de?nitions (continued) complete register id string a3 a2 a1 a0 s2 s1 s0 r/ w a kvco 0.25 2 w n ----------------------------------------------
1996 may 29 41 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a control operating mode register #2 (cm2) 0 0 00011006h bits 7-4 km3-0 equalizer outer tap coef?cient km2 km2 = 0.0168 * km (km is in 2's compliment) 0111 = +0.117 0110 = +0.101 0101 = +0.0840 0100 = +0.0672 0011 = +0.0504 0010 = +0.0336 0001 = +0.0168 0000 = 0 1111 = -0.0168 1110 = -0.0336 1101 = -0.0504 1100 = -0.0672 1011 = -0.0840 1010 = -0.1010 1001 = -0.1170 1000 = -0.1350 bit 3 tme test mode enable 0 = tpc and tpd active when sg = 1 and bit 7 of power down control register is 1 1 = tpc and tpd as set by bits 6 and 7 of the power down control register bit 2 pfspol precoder force state 0 = precoder state set to 0 1 = precoder state set to 1 bits 1-0 qtc1-0 qasym and q time constant control (tme = 1) qasym q 00 = 100 ns 50 ns 01 = 200 ns 100 ns 10 = 400 ns 200 ns 11 = 800 ns 400 ns bit 0 pcfdis precoder force disabled (tme = 0) 0 = precoder initialization enabled 1 = precoder initialization disabled serial port register de?nitions (continued) complete register id string a3 a2 a1 a0 s2 s1 s0 r/ w
1996 may 29 42 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a pin descriptions power supply pins pin name type pin function vpa - agc / filter analog circuit supply vpf - time base generator pll ecl plus write pre-comp supply (connect to analog supply) vpt - time base generator pll analog circuit supply vpp - data separator pll analog circuit supply vpd - ttl buffer i/o digital supply vpc - internal ecl, cmos logic digital supply vps - sampled data processor supply vna - agc / filter analog circuit ground vnf - time base generator ecl ground (connect to analog ground) vnt - time base generator pll analog circuit ground vnp - data separator pll analog circuit ground vnd - ttl buffer i/o digital ground vnc - internal ecl, cmos logic digital ground vns - sampled data processor ground analog input pins pin name type pin function via+, via- i agc amplifier inputs: differential agc ampli?er input pins analog output pins pin name type pin function tpa+, tpa- o test pins: emitter output test points. various signals are multiplexed to these test points by the test point control register. the signals include the equalizer control voltage and output, various timing loop control signals and the viterbi survival register outputs. the test points are provided to show how the signal is being processed. internal "pull down" resistors to ground are provided. to save power when not in test mode, the control test register bits 3-5 must be set to "0". tpb+, tpb- o test pins: emitter output test points similar to tpa+ and tpa-. the pins are used to look at the other phase of the interleaved signals. tpc+, tpc- o test pins: bi-directional test points which provide emitter outputs similar to tpa+ and tpa- and provide differential input capability. the pins are used to look at the normal outputs of the continuous time ?lter or the agc ampli?er output. these pins can also be driven with dp/dn like signals for back end testing. tpd+, tpd- o test pins: bi-directional test points which provide emitter output test points similar to tpa+ and tpa- and provide differential input capability. the pins are used to look at the differentiated outputs of the continuous time ?lter or the agc ampli?er output. these pins can also be driven with cp/cn like signals for back end testing. tpe o test pin: emitter output test point similar to tpa+. provides servo fwr out when enabled.
1996 may 29 43 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a analog output pins (continued) pin name type pin function ato o analog test out: this test point output provides a monitor of one of three signals. they are the equalizer quality signal, the amplitude asymmetry signal, and the dac outputs. the selected output is determined by the programming of the atosel bits in the power down register. if the dac outputs are selected, the last dac written to by the serial control register is the dac monitored. signal at ato is referenced to maxref/2. burst a, burst b, burst c, burst d o servo outputs: these outputs are the ampli?ed and offset versions of the voltages captured on the servo hold capacitors. they are offset by an internally generated 0.27v baseline. maxref o servo reference output: +3.2v dc reference voltage that represents the maximum output voltage for the a, b, c, and d outputs. can be used as the reference for an external a/d converter. analog control pins pin name type pin function byp - the data agc integrating capacitor, c byp , is connected between byp and vpa. this pin is used when not in servo read mode (sg = 0). byps - the servo agc integrating capacitor, c byps , is connected between byps and vpa. this pin is used when in servo read mode (sg = 1). fltr1+, fltr1- - tbg pll loop filter: differential connection points for the time base generator pll loop ?lter components. fltr2+, fltr2- - ds pll loop filter: differential connection points for the data separator pll loop ?lter capacitor. rr - current reference resistor input: an external 1%, 10 k w (for max data rate of 125 mbit/s) or 12.1 k w (for max data rate of 100 mbit/s) resistor is connected from this pin to ground to establish a precise internal reference current for the data separator and the time base generator dacs. vrx - filter reference resistor input: an external 1%, 12.1 k w resistor is connected from this pin to ground to establish a precise ptat (proportional to absolute temperature) reference current for the ?lter dacs. vrc - agc reference voltage: vrc is derived by a bandgap reference from vpa. wrdel - lowz one-shot adjust: the resistor connected between this pin and gnd determines the length of the lowz period. t lz = r lz * 0.1 m s/k w . agcdel - fast recovery one-shot adjust: the resistor connected between this pin and gnd determines the length of the fast decay period. t fr = r fr * 0.1 m s/k w . agcrst - ultra fast decay current adjust: the resistor connected between this pin and vpa determines the ultra fast decay current given by the equation i = (vpa - vbyp)/rufd. this pin may be left open if ultra fast decay action is not required.
1996 may 29 44 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a digital input pins pin name type pin function lowz i low-z mode input: ttl compatible cmos control pin which, when pulled high, the input impedance is reduced to allow rapid recovery of the input coupling capacitor. when pulled low, keeps the agc ampli?er and ?lter input impedance high. an open pin is a logic high. fastrec i fast recovery: ttl compatible cmos control pin which, when pulled high, puts the agc charge pump in the fast decay mode. an open pin is a logic high. pdwn i power down control: cmos compatible power control pin. when set to logic low, the entire chip is in sleep mode with all circuitry, except serial port, shut down. this pin must be set to logic high in normal operating mode. selected circuitry can be shut down by the power down register. the pdwn pin must be either driven to a valid cmos high level or externally pulled up since it is not internally pulled up. hold i agc hold control input: ttl compatible cmos control pin which, when pulled low, holds the agc ampli?er gain constant by turning off the agc charge pump. the agc loop is active when this pin is either at high or open. eqhold i equalizer hold control input: ttl compatible control pin which, when pulled high causes the present adaptive equalizer tap weights to be held until the input is set low. an open pin is at logic high. fref i reference frequency input: reference frequency for the time base generator. fref may be driven either by a direct coupled ttl signal or by an ac coupled ecl signal. when bit 3 (bt) of the control operating register is set, fref replaces the vco as the input to the data separator. wclk i write clock: ttl compatible cmos input that latches in the data at the selected nrz interface on the rising edge. must be synchronous with the write data nrz input. for short cable delays, wclk may be connected directly to pin rclk. for long cable delays, wclk should be connected to an rclk return line matched to the nrz data bus line delay. an open pin is at logic high. rg i read gate: ttl compatible cmos input that, when pulled high, selects the pll reference input and initiates the pll synchronization sequence. a high level selects the rd input and enables the read mode/address detect sequences. a low level selects the time base generator output. an open pin is at logic high. wg/ wg i write gate: ttl compatible cmos input that, when pulled high, enables the write mode. the active state of wg/ wg can be selected by the wgp bit in the control operating register. an open pin is at logic high. sg i servo gate: ttl compatible cmos input that, when pulled high, enables the servo read mode. an open pin is at logic high. vrdt i viterbi read data: a ttl or ac coupled pecl compatible input to the data separator back end, for testing purposes only. this pin is controlled by the vrdt bit in the control test register. dwr i direct write mode 2 enable: enables dwi, dwi inputs to the write data ?ip-?op when input is low. ttl compatible cmos levels. open pin is at logic high.
1996 may 29 45 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a digital input pins (continued) pin name type pin function dwi, dwi i direct write inputs: inputs connect to the toggle input of the write data ?ip-?op when dwr is low. pecl input levels. can be left open. strobe i servo strobe input: active high enable for charging of an individual hold capacitor during a servo burst capture. the falling edge of strobe will increment an internal counter that determines which of the four hold capacitors will be charged during the next strobe pulse. ttl compatible cmos levels. open pin is at logic high. reset i reset control input: active low reset for discharging of the four internal servo burst hold capacitors for channels a, b, c, and d. ttl compatible cmos input levels. open pin is at logic high. digital bi-directional pins pin name type pin function nrz0-7 i/o byte wide nrz data port: ttl compatible cmos bi-directional input/output. input to the encoder when wg/ wg is high. output from the decoder when rg is high. the 4 lsbs are used in nibble mode. the 4 msbs can be left open if not used. nrzp i/o nrz data parity bit: active when in byte-wide mode. ttl compatible cmos bi-directional input / output. generates even read parity when rg is high, and accepts even write parity when wg/ wg is active. can be left open if not used. digital output pins pin name type pin function rclk o read reference clock: a multiplexed clock source used by the controller. when rg is low, rclk is synchronized to the time base generator output, f tbg . when rg goes high, rclk remains synchronized to f tbg until the sfc is reached. at that time, rclk is synchronized to the data separator vco. during a mode change, no glitches are generated and no more than one lost clock pulse will occur. limited swing cmos output levels. sbd o sync byte detect: transitions low upon detection of sync byte. this transition is synchronous with the sync byte's placement on the nrz lines. once it transitions low, sbd remains low until rg goes low, at which point it returns high. cmos output. wd, wd o write data: write data ?ip-?op output. the data is automatically re-synchronized (independent of the delay between rclk and wclk) to the reference clock f tbg , except in direct write mode 2. differential pecl output levels. rds/ rds o servo read data: read data pulse output for servo read data. active low limited swing cmos output. output active when sg is high, and high when sg is low. the rds/ rds output becomes active high if the servo mode select bit (sms) in the data rate register is set. ppol o servo read data polarity: read data pulse polarity output for servo read data. active high limited swing cmos output. negative pulse = low, positive pulse = high. output active when sg is high. perr o parity error detect: transitions high when a parity error is detected at the byte wide nrz interface. cmos output.
1996 may 29 46 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a serial port pins pin name type pin function sclk i serial data clock: positive edge triggered clock input for the serial data. cmos input levels. sdata i serial data: input pin for serial data; 8 register select bits ?rst, followed by 8 data bits. the register select bits and data bits are entered lsb ?rst, msb last. cmos input levels. sden i serial data enable: a high level input enables data loading. the data is internally parallel latched when this input goes low. cmos input levels.
1996 may 29 47 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a unless otherwise specified, the recommended operating conditions are as follows: 4.5v < positive supply voltage < 5.5v, 0 c < t amb < 55 c for 100-lead lqfp and 25 c < t j < 135 c. currents flowing into the chip are positive. current maximums are currents with the highest absolute value. electrical specifications absolute maximum ratings operation beyond the maximum ratings may damage the device symbol parameter rating vp positive 5.0v supply voltage -0.5 to 7v storage temperature -65 to 150 c solder vapor bath 215 c, 90s, 2 times junction operating temperature +135 c output pins 10 ma analog pins 10 ma voltage applied to other pins -0.3v to vp+0.3v recommended operating conditions power supply current and power dissipation symbol parameter test conditions min. nom. max. unit i cc supply current (vpn) outputs and test point pins open t amb = 27 c 185 ma pd power dissipation normal mode outputs and test point pins open, t amb = 27 c 925 1500 mw pwr data separator off power down register = 2d 530 760 mw pwr data separator off and tbg off power down register = 6d 460 685 mw pwr idle through serial port power down register = 7d 125 165 mw sleep mode pdwn = low 5 mw
1996 may 29 48 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a digital inputs ttl c ompatible cmos i nputs fref and vrdt i nputs cmos i nputs p seudo ecl c ompatible i nputs digital outputs cmos outputs d igital d ifferential o utputs (wd, wd) symbol parameter test conditions min. nom. max. unit v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 vpd+0.3 v i il input low current v il = 0.4v -400 m a i ih input high current v ih = 2.4v 100 m a symbol parameter test conditions min. nom. max. unit v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 vpd+0.3 v i ilf input low current v il = 0.4v -400 m a i ihf input high current v ih = 2.4v 500 m a symbol parameter test conditions min. nom. max. unit v ilc input low voltage vpc = 5.0v 1.5 v v ihc input high voltage vpc = 5.0v 3.5 v symbol parameter test conditions min. nom. max. unit v il input low voltage vpd-2.0 v ih -0.25 v v ih input high voltage vpd-1.1 vpd-0.4 v input current -100 +100 m a symbol parameter test conditions min. nom. max. unit v olc output low voltage i ol = +2 ma 0.45 v v ohc output high voltage i oh = -100 m a 0.7 * vpd v symbol parameter test conditions min. nom. max. unit v old output low voltage i ol = 2 ma vpd-1.9 v ohd -0.3 v v ohd output high voltage i oh = 2 ma vpd-1.4 vpd-0.5 v output sink current -3.5 ma differential voltage | v(wd) - v( wd) | 0.6 vppd
1996 may 29 49 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a t est p oint o utput l evels serial port timing refer to figure 16. symbol parameter test conditions min. nom. max. unit test point output swing tpa+, tpa- tpb+, tpb- 0.8 vppd tpc+, tpc- tpd+,tpd- tpe c load = 5 pf 1.0 vpa-1.5 v ato test point r load 3 10k w relative to maxref/2 -0.6 1.2 v source impedance tpa+/tpa- tpb+/tpb- tpc+/tpc- tpd+/tpd- tpe, ato 45 w output current tpc+/tpc- tpd+/tpd- tpe -0.8 +3 ma tpa+/tpa- tpb+/tpb- -3 +1 ato -2 +2 common voltage tpc+/tpc- tpd+/tpd- tpe 2.5 v tpa+/tpa- tpb+/tpb- vpa-1.7 -2vbe ato maxref/2 symbol parameter test conditions min. nom. max. unit t c sclk data clock period, 80 ns t ckl sclk low time sclk < 0.8v 30 ns t ckh sclk high time sclk > 2.0v 30 ns t sens enable to sclk 40 ns t senh sclk to disable 40 ns t ds data set-up time 15 ns t dh data hold time 15 ns t sl sden min. low time 160 ns
1996 may 29 50 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a agc characteristics unless otherwise speci?ed, recommended operating conditions apply. agc a mplifier the input signals are ac coupled to via+ and via-. integrating capacitor c byp = 1000 pf, is connected between byp and vpa. integrating capacitor c byps = 1000 pf, is connected between byps and vpa. unless otherwise specified, the output is measured differentially at tpc+ and tpc-, fin = 5 mhz, the filter frequency | c = max and the filter boost = 0 db. all specifications apply equally to servo and read mode prior to sfc. symbol parameter test conditions min. nom. max. unit input range filter boost =0 db @ | c 4 mhz | c 34 mhz, fin = | c 20 250 mvppd input range filter boost =11 db @ | c 9 mhz | c 34 mhz, fin = | c 20 200 mvppd on on voltage measured @ tpc via = 20 to 250 mvppd 1,1,-1,-1,--- pattern dp/dn output selected 5 mhz < | c < 34 mhz, fin = | c boost = 0 to 13 db 1.19 1.40 1.61 vppd dp/dn voltage variation 20mvppd < via < 250mvppd 5.0 % gain range 3 64 v/v gain sensitivity byp or byps voltage change 38 db/v r in differential input resistance lowz = low, lztc = low lowz = low, lztc = high lowz = high, lztc = x 5.8 1.7 200 7.6 2.7 550 9.4 4.0 1050 k w k w w single-ended input resistance lowz = low, lztc = low lowz = low, lztc = high lowz = high, lztc = x 6.5 1.9 500 k w k w w v oo output offset change from gain = 3 v/v to 64 v/v with dc cancellation off 200 mv e in input noise voltage fixed gain = 24 db, rs = 0 w 15 30 nv/ ? hz cmrr common mode rejection fixed gain = 24 db, rs = 0 w 35 db psrr power supply rejection fixed gain = 24 db, rs = 0 w 40 db
1996 may 29 51 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a agc control section the input signals are dc coupled into tpc with tpc selected as inputs. pulse quali?er characteristics unless otherwise specified, a 100 mvpp sine wave at 15 mhz is ac coupled into via . fc = 127, and fb = 0. d ual l evel q ualifier see above for input conditions unless otherwise specified. symbol parameter test conditions min. nom. max. unit i d decay current normal fastrec = low, sg = low dr = data rate register 37 < dr < 127 rr = 12.1 k w -24.5 m a servo mode decay current normal fastrec = low, sg = high tpc+ = tpc- -24.5 m a i dfr fast decay current fastrec = high tpc+ = tpc- 8 * i d a i ch normal attack current |tpc+ - tpc-| = 0.7875v fastrec = low -17 * i d a i chf fast attack current |tpc+ - tpc-| 3 1.09v fastrec = low -143 * i d a i chfr fast recovery attack current |tpc+ - tpc-| = 0.7875v fastrec = high -64 * i d a sample data agc peak charge and discharge currents 0 agc 3 agc = agc1-0 dr = data rate register 37 < dr <127, rr(k w ) +/-2.66 * 10 -6 * agc * dr/rr a byp pin leakage current hold = low, v byp = vrc -70 +50 na byps pin leakage current hold = low, v byps = vrc -70 +50 na vrc reference voltage -50 m a io +500 m a vpa - 2.56 vpa + 2.1 v symbol parameter test conditions min. nom. max. unit l th data level threshold prior to sfc l th (mv) = 10.47 * ld 16 ld 63 l th -11% l th l th +11% v after sfc ale = 0 l th (mv) = 7.44 * ld ale = 1 l th (mv) = 1.574 * ld 16 ls 63 l th -11% l th l th +11% v ls th servo level threshold ls th (mv) = 10.47 * ls 16 ls 63 ls th -11% ls th ls th +11% v rds/ rds pulse width high voltage rdspw = 0 7.7 15 20 ns rdspw = 1 16.8 27 35 ns
1996 may 29 52 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a v iterbi q ualifier see general for input conditions unless otherwise specified. e qualization q uality f actor unless otherwise specified, measured at ato pin loaded with 5 pf. via input signal has no asymmetry. measured after training sequences. continuous training pattern with zeros displaced by 10% of one's magnitude of 500 mv a mplitude a symmetry q uality f actor unless otherwise specified, measured at ato pin loaded with 5 pf. via input signal has 10% amplitude asymmetry. asymmetry (%) = ((v +1 -v -1 )/(v +1 +v -1 )) * 100, where v +1 = positive "1" sample value and v -1 = negative "1" sample value. this is measured with continuous training bytes, 93h, with distance between canceled and non-canceled zeros at 10 % of one's magnitude of 500 mv or 100 mv. d ual l evel q ualifier (continued) symbol parameter test conditions min. nom. max. unit ppol to rds/ rds delay time ppol edge to rds/ rds rise/fall, measured at 1.5v crossing 2.5 12 ns ppol, rds/ rds rise time 15 pf load, 0.8 to 2.4v 8 ns ppol, rds/ rds fall time 15 pf load, 2.4 to 0.8v 6 ns pulse pairing window and hysteresis ls th = 50%. measured at the rising/falling edge of rds/ rds fin = 5 mhz, fcs = 30 -2.5 +2.5 ns symbol parameter test conditions min. nom. max. unit v th viterbi threshold voltage v th (mv) = 7.874 * vd 45 vd 127 v th - 10% v th v th +10% v symbol parameter test conditions min. nom. max. unit reference voltage no pulse asymmetry atosel1-0 = 00 typ.-130mv maxref/2 typ.+130mv v q absolute deviation of zeros is multiplied by gain 600 mv drift 0.2 mv/ m s symbol parameter test conditions min. nom. max. unit reference voltage atosel1-0 = 00 typ.-100mv maxref/2 typ.+100mv v qasym at ato 400 mv
1996 may 29 53 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a ato b uffer c haracteristics unless otherwise specified, measured at ato pin loaded with 5 pf. via input signal has no asymmetry. i nternal ac c oupler c haracteristics measured at tpc+/tpc- and tpd+/tpd- pins. programmable filter characteristics unless otherwise specified, recommended operating conditions apply. the input signals are ac coupled to via+ and via-. all specifications identical for identical data and servo register settings. data uses c byp from byp to vpa and servo uses c byps from byps to vpa. symbol parameter test conditions min. nom. max. unit reference voltage atosel 1-0 = 00 typ. - 100 maxref/2 typ. +100 v swing from reference voltage +/-0.6 v source impedance 50 w drive capability +/- refers to source/sink +2/-2 +5/-3 ma symbol parameter test conditions min. nom. max. unit offset voltage accpl = 0 -35 +35 mv lowz time constant lowz = 1, lztc = x 0.3 m s non lowz time constant lowz = 0, lztc = 0 5 m s lowz = 0, lztc = 1 1.5 m s symbol parameter test condition min. nom. max. unit | cr filter cutoff range | c (mhz) = 0.301 * fc - 1.142 44 fc 117 | c (mhz) = 0.277 * fcs - 0.08 14 fc 43 0 db boost 4-34 mhz | ca filter | c accuracy 44 fc 127 14 fc 43 -15 -20 +15 +20 % od gain to on gain mismatch | in = 0.67 * | c 0 db boost mismatch = % -20 +20 % boost @ fc boost (db) = 20 * log [0.021848 * fb + 0.000046 * fb * fc +1] fb db boost accuracy boost = 13 db -2.0 +2.0 db boost = 9 db -1.7 +1.7 db filter output dynamic range on thd = 2.5%, | in = 0.67 * | c, c l = 15 pf 1.4 vpp odgain ongain C ongain -------------------------------------------------- - 100
1996 may 29 54 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a transversal filter characteristics programmable filter characteristics (continued) symbol parameter test condition min. nom. max. unit tgd variation | c = 34 mhz fin = 0.3 | c to | c fb = 0 | c = 34 mhz fin = 0.3 | c to | c fb = 127 | c = 12 mhz to 34 mhz fin =0.3 | c to | c 0 fb 127 | c = 4 mhz to 12 mhz fin = 0.3 | c to | c 0 fb 127 | c = 12 mhz to 34 mhz fin = | c to 1.75 | c 0 fb 127 | c = 4 mhz to 12 mhz fin = | c to 1.75 | c 0 fb 127 -500 -700 -3 -4 -3 -6 +500 +700 +3 -4 +3 +6 ps ps % % % % on+ - on- output noise voltage, no boost bw=100 mhz, rs=50 w | c = 34 mhz, boost = 0 db agc gain = 24 db ?xed 3.4 mv rms on+ - on- output noise voltage, max. boost bw=100 mhz, rs=50 w | c = 34 mhz; fb = 127 agc gain = 24 db ?xed 6.8 mv rms vrx rx pin voltage t amb = 27 c t amb = 127 c 600 800 mv mv rx resistance 1% ?xed value 12.1 k w symbol parameter test conditions min. nom. max. unit km1 range 0.15 0.2 v/v km1 gain drift eqhold = 1 hold time < 1 ms 0.015 0.05 v/v/ms km2 range +0.13125 -0.15 km2 resolution 0.01875 km2 accuracy 20 % note: km1 and the equalizer control voltage at tpa+ - tpa- is approximately related by km1 = 0.009 * data rate (mbit/s) * (tpa+ - tpa-).
1996 may 29 55 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a time base generator characteristics rr = 10.0 k w to gnd for 125 mbit/s max. operation, and 12.1 k w for 100 mbit/s max. operation symbol parameter test conditions min. nom. max. unit fref input range control operating register bt bit = 0 6 25 mhz control operating register bt bit = 1 and control test register efr bit =1 141 mhz fref input pulse width control operating register bt bit = 0 10 ns control operating register bt bit = 1 and control test register efr bit =1 2ns f tbg frequency range 47 141 mhz f tbg jitter > 10k samples 30 200 ps rms m counter range 2 255 n counter range 2 127 f tbg vco center frequency fltr1+ - fltr1- = 0v f tbg =[(1.143 * dr) + 4.986] mhz rr = 10.0 k w 0.80 * f tbg 1.20 * f tbg mhz f tbg =[(0.948 * dr) + 1.831] mhz rr = 12.1 k w vco dynamic range -2.0v < fltr1+ - fltr1- < +2.0v f tbg = 94 mhz +25 % kvco vco control gain w i =2 p * f tbg -2.0v < fltr1+ - fltr1- < 2.0v 0.12 * w i 0.18* w i 0.24 * w i rad/(v.s) kd phase detector gain kd = (2.125 * dr) + 3.171 rr = 10 k w 0.72 * kd 1.22 * kd m a/rad kd = (1.777 * dr) + 3.335 rr = 12.1 k w kvco * kd product accuracy -28 +28 %
1996 may 29 56 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a data separator characteristics unless otherwise specified, recommended operating conditions apply. read mode - byte-wide (refer to fig. 22) symbol parameter test conditions min. nom. max. unit t rrc read clock rise time 0.8v to 2.4v c l < 15 pf 10 ns t frc read clock fall time 2.4v to 0.8v c l < 15 pf 10 ns t rd rclk pulse width except during re-sync 4/9t orc -5 4/9t orc +5 ns t dc1 rclk re-sync period at sfc and rg falling edge measured from rising edge to rising edge of rclk t orc t orc + 2tc ns t dc2 rclk re-sync period at code boundary detect measured from rising edge to rising edge of rclk t orc 2t orc ns t ns , t nh nrzx out set-up and hold time 20 ns t sbs sbd set-up time 20 ns figure 22: byte-wide read timing 9 t c 4 t c t rd vco clk rclk nrz07 nrzp sbd t orc t frc t rrc 2.4v 0.8v 2.4v 0.8v 1.5v 1.5v 1.5v (sb2) 1.5v (dt0) t ns t nh 1.5v t sbs sm00004
1996 may 29 57 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a write mode - byte-wide (refer to fig. 23) write data output (refer to fig. 24) read mode - nibble symbol parameter test conditions min. typ. nom. unit t rwc write clock rise time 0.8 to 2.0 v c l < 15 pf 10 ns t fwc write clock fall time 2.0 to 0.8 v c l < 15 pf 8ns t snrz nrzx set-up time 10 ns t hnrz nrzx hold time 3 ns t perr measured from the rising edge of wclk to the transition of perr 41 ns symbol parameter test conditions min. typ. max. unit t wd write data output position accuracy write precomp = 0, c l < 15 pf, t tbg = 1/f tbg t tbg - 0.5 t tbg + 0.5 ns t rwd write data output rise time 20% to 80% points 4 ns t fwd write data output fall time 80% to 20% points 4 ns symbol parameter test conditions min. nom. max. unit t rcl rclk low time c l < 15 pf 5 ns t rch rclk high time c l < 15 pf 5 ns t rrc read clock rise time 0.8v to 2.4v c l < 15 pf 8ns t frc read clock fall time 2.4v to 0.8v c l < 15 pf 6ns t ns , t nh nrzx out set-up and hold time 5.6 ns t sdl sbd fall to rclk rising c l < 15 pf 7.5 ns figure 23: write mode nrz interface timing (byte-wide and nibble modes) wclk nrz07 nrzp t wc t rwc 2.0v 0.8v 1.5v 1.5v 1.5v 1.5v t snrz t hnrz t fwc 2.0v 0.8v t wch t wcl perr v cc /2 parity error of adt1o t perr adt1o 1.5v sm00027 0.8v
1996 may 29 58 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a write mode - nibble (refer to fig. 23) write precompensation symbol parameter test conditions min. nom. max. unit t wc wclk period c l < 15 pf 24 ns t wcl wclk low time c l < 15 pf 5 ns t wch wclk high time c l < 15 pf 5 ns t rwc write clock rise time 0.8 to 2.0 v c l < 15 pf 10 ns t fwc write clock fall time 2.0 to 0.8 v c l < 15 pf 8ns t snrz nrzx set-up time 8 ns t hnrz nrzx hold time 3 ns symbol parameter test conditions min. nom. max. unit tpc write precomp time shift as a percentage of t tbg tpc = 2.1 * wpc 0 < wpc < 15 0.8 * tpc 1.2 * tpc % figure 24: nibble read timing t rrc 2.4v 0.8v t frc 2.4v 0.8v t rch t rcl 2.4v 1.5v 1.5v 2 t c 5 t c 4 t c t rd 1.5v 1.5v t ns t nh sb2(7:4) sb2(3:0) vco clk rclk nrz03 sbd sm00006 t sdl 1.5v
1996 may 29 59 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a data synchronizer pll symbol parameter test conditions min. nom. max. unit fvco vco center frequency fl tr2+ - fltr2- = 0v fvco = [(1.143 * dr) + 4.986] mhz rr = 10.0 k w fvco = [(0.948 * dr) + 1.831] mhz rr = 12.1 k w 0.8 * fvco 1.2 * fvco ns vco dynamic range in each direction -2.0v < fltr2+ - fltr2- < +2.0v +25 % vco control gain and m, m * kvco w i =2 p /fvco m = 4.32 * (dr/127) rr = 10.0 k w m = 3.60 * (dr/127) rr = 12.1 k w -0.25v < fltr2+ - fltr2- < +0.25v 0.11 * w i * m 0.29 * w i * m rad/(v-s) charge pump transconductance gm = 350 m a/v during synchronization 0.6 * gm 1.4 * gm a/v kdi idle mode phase detector gain kdi = 0.15 gm * m rr = 10.0 k w kdi = 0.18 gm * m rr = 12.1 k w kdi m a/rad gm * m * kvco product accuracy -28 +28 % a * kvco product accuracy a= 0.8 * (drc/127) -30 +30 %
1996 may 29 60 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a servo characteristics unless otherwise specified input is 15 mhz sine wave into dp/dn inputs, tpc/d1-0 = 01. sms = 0. strobe and reset durations are 1.0 m s and sbcc = 10. symbol parameter test conditions min. nom. max. unit maxref output voltage i source = 0 ma 3.06 3.22 3.42 v maxref load regulation i source < 1.5 ma 40 mv a, b, c, d output resistance i source / i sink = 0.1 ma 50 w a, b, c, d output low voltage i sink = 0.1 ma reset = low 170 270 370 mv a, b, c, d output swing dp/dn = 1.4 vpp 2.56 2.8 3.01 v a, b, c, d gain 0.3 1996 may 29 61 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a P32P4910a pinout 100 lqfp burst d burst c burst b burst a 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 12 11 44 43 42 41 21 22 25 40 39 37 38 36 35 34 23 24 48 47 46 45 50 49 52 51 56 55 54 53 60 59 58 57 91 92 93 94 95 96 97 98 99 100 26 27 28 29 30 31 32 33 61 62 64 63 65 66 75 74 73 72 71 70 69 68 67 81 82 83 84 85 86 87 88 89 90 80 79 76 78 77 via+ fltr1+ via- bypd hold lowz fastrec vrdt sclk sdata sden vpf fref vnf vpt dwi vnt dwi vpa vna sg tpe vrx nc tpd+ agcrst agcdel wrdel nc nc eqhold ato vps vrc rr maxref reset strobe tpb+ tpb- vns ppol nc wd wd nc wg/ wg fltr1- vps vns tpa+ tpa- vpp fltr2+ fltr2- vnp vnc vpc nc nc nrz2 dwr nrz1 nrz0 pdwn perr nc nrzp rg nrz3 nc vnd vpd nrz4 nrz5 nrz6 nrz7 wclk rclk sbd nc nc nc nc byps nc nc nc nc rds/ rds nc nc tpd- tpc+ tpc- nc
1996 may 29 62 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a lqfp100: plastic low pro?le quad ?at package; 100 leads; body 14 x 14 x 1.4 mm sot407-1 figure 25: package diagram
1996 may 29 63 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a notes
1996 may 29 64 philips semiconductors product speci?cation prml read channel with pr4, 8/9 endec, 4-burst servo P32P4910a definitions data sheet identi?cation product status de?nition objective speci?cation formative or in design this data sheet contains the design target or goal speci?cations for product development. speci?cations may change in any manner without notice. preliminary speci?cation preproduction product this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation full production this data sheet contains final speci?cations. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appliances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonably be expected to result in a personal injury. philips semiconductors and philips corporation product can reasonably be expected to result in a personal injury. philips semiconductors and philips electronics of north america corporation customers using or selling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics of north america corporation for any damages resulting from such improper use or sale. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 94088-3409 telephone 800-234-7381 philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a.

▲Up To Search▲

Price & Availability of P32P4910

	To Download P32P4910 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .